Search

Marian C. Knode

Examiner (ID: 10867)

Most Active Art Unit
1808
Art Unit(s)
1808, 1643, 1764, 1806
Total Applications
291
Issued Applications
149
Pending Applications
29
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1409882 [patent_doc_number] => 06528407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Process for producing electrical-connections on a semiconductor package, and semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/684410 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528407.pdf [firstpage_image] =>[orig_patent_app_number] => 09684410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684410
Process for producing electrical-connections on a semiconductor package, and semiconductor package Oct 5, 2000 Issued
Array ( [id] => 1414754 [patent_doc_number] => 06521529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'HDP treatment for reduced nickel silicide bridging' [patent_app_type] => B1 [patent_app_number] => 09/679880 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521529.pdf [firstpage_image] =>[orig_patent_app_number] => 09679880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679880
HDP treatment for reduced nickel silicide bridging Oct 4, 2000 Issued
Array ( [id] => 1376362 [patent_doc_number] => 06559051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors' [patent_app_type] => B1 [patent_app_number] => 09/679881 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6694 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559051.pdf [firstpage_image] =>[orig_patent_app_number] => 09679881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679881
Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Oct 4, 2000 Issued
Array ( [id] => 7643915 [patent_doc_number] => 06429123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method of manufacturing buried metal lines having ultra fine features' [patent_app_type] => B1 [patent_app_number] => 09/679270 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3015 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429123.pdf [firstpage_image] =>[orig_patent_app_number] => 09679270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679270
Method of manufacturing buried metal lines having ultra fine features Oct 3, 2000 Issued
Array ( [id] => 1299854 [patent_doc_number] => 06624076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/672860 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 6149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624076.pdf [firstpage_image] =>[orig_patent_app_number] => 09672860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672860
Semiconductor device and method for fabricating the same Sep 28, 2000 Issued
Array ( [id] => 1402034 [patent_doc_number] => 06534388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method to reduce variation in LDD series resistance' [patent_app_type] => B1 [patent_app_number] => 09/670330 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2577 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534388.pdf [firstpage_image] =>[orig_patent_app_number] => 09670330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670330
Method to reduce variation in LDD series resistance Sep 26, 2000 Issued
Array ( [id] => 1163321 [patent_doc_number] => 06759314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method for manufacturing semiconductor devices using thermal nitride films as gate insulating films' [patent_app_type] => B1 [patent_app_number] => 09/670520 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 6540 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759314.pdf [firstpage_image] =>[orig_patent_app_number] => 09670520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670520
Method for manufacturing semiconductor devices using thermal nitride films as gate insulating films Sep 25, 2000 Issued
Array ( [id] => 1435870 [patent_doc_number] => 06355513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Asymmetric depletion region for normally off JFET' [patent_app_type] => B1 [patent_app_number] => 09/669480 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3766 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355513.pdf [firstpage_image] =>[orig_patent_app_number] => 09669480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669480
Asymmetric depletion region for normally off JFET Sep 24, 2000 Issued
Array ( [id] => 1402372 [patent_doc_number] => 06534406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method for increasing inductance of on-chip inductors and related structure' [patent_app_type] => B1 [patent_app_number] => 09/668790 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534406.pdf [firstpage_image] =>[orig_patent_app_number] => 09668790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668790
Method for increasing inductance of on-chip inductors and related structure Sep 21, 2000 Issued
Array ( [id] => 1264586 [patent_doc_number] => 06660646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method for plasma hardening photoresist in etching of semiconductor and superconductor films' [patent_app_type] => B1 [patent_app_number] => 09/668250 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1250 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660646.pdf [firstpage_image] =>[orig_patent_app_number] => 09668250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668250
Method for plasma hardening photoresist in etching of semiconductor and superconductor films Sep 20, 2000 Issued
Array ( [id] => 1553385 [patent_doc_number] => 06348356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors' [patent_app_type] => B1 [patent_app_number] => 09/664636 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348356.pdf [firstpage_image] =>[orig_patent_app_number] => 09664636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664636
Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors Sep 18, 2000 Issued
Array ( [id] => 1235714 [patent_doc_number] => 06689668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Methods to improve density and uniformity of hemispherical grain silicon layers' [patent_app_type] => B1 [patent_app_number] => 09/652650 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6137 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689668.pdf [firstpage_image] =>[orig_patent_app_number] => 09652650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652650
Methods to improve density and uniformity of hemispherical grain silicon layers Aug 30, 2000 Issued
Array ( [id] => 4322217 [patent_doc_number] => 06331493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Process for making low dielectric constant dielectric films' [patent_app_type] => 1 [patent_app_number] => 9/653299 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6834 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331493.pdf [firstpage_image] =>[orig_patent_app_number] => 653299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653299
Process for making low dielectric constant dielectric films Aug 30, 2000 Issued
Array ( [id] => 1588890 [patent_doc_number] => 06482724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Integrated circuit asymmetric transistors' [patent_app_type] => B1 [patent_app_number] => 09/652900 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2648 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482724.pdf [firstpage_image] =>[orig_patent_app_number] => 09652900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652900
Integrated circuit asymmetric transistors Aug 30, 2000 Issued
Array ( [id] => 1390981 [patent_doc_number] => 06544902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Energy beam patterning of protective layers for semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/652340 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4508 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544902.pdf [firstpage_image] =>[orig_patent_app_number] => 09652340 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652340
Energy beam patterning of protective layers for semiconductor devices Aug 30, 2000 Issued
Array ( [id] => 1399092 [patent_doc_number] => 06537891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Silicon on insulator DRAM process utilizing both fully and partially depleted devices' [patent_app_type] => B1 [patent_app_number] => 09/650081 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3926 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537891.pdf [firstpage_image] =>[orig_patent_app_number] => 09650081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650081
Silicon on insulator DRAM process utilizing both fully and partially depleted devices Aug 28, 2000 Issued
Array ( [id] => 1071893 [patent_doc_number] => 06841477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Metal interconnection, semiconductor device, method for forming metal interconnection and method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/648750 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 55 [patent_no_of_words] => 13700 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841477.pdf [firstpage_image] =>[orig_patent_app_number] => 09648750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648750
Metal interconnection, semiconductor device, method for forming metal interconnection and method for fabricating semiconductor device Aug 27, 2000 Issued
Array ( [id] => 1410387 [patent_doc_number] => 06528435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Plasma processing' [patent_app_type] => B1 [patent_app_number] => 09/648730 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528435.pdf [firstpage_image] =>[orig_patent_app_number] => 09648730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648730
Plasma processing Aug 24, 2000 Issued
Array ( [id] => 1385950 [patent_doc_number] => 06548368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of forming a MIS capacitor' [patent_app_type] => B1 [patent_app_number] => 09/644941 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4150 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548368.pdf [firstpage_image] =>[orig_patent_app_number] => 09644941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644941
Method of forming a MIS capacitor Aug 22, 2000 Issued
Array ( [id] => 1381122 [patent_doc_number] => 06551846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration' [patent_app_type] => B1 [patent_app_number] => 09/642751 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 17524 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551846.pdf [firstpage_image] =>[orig_patent_app_number] => 09642751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642751
Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration Aug 17, 2000 Issued
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