Search

Marianne Dibrino

Examiner (ID: 5127)

Most Active Art Unit
1644
Art Unit(s)
1644, 1641
Total Applications
1213
Issued Applications
352
Pending Applications
240
Abandoned Applications
638

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20690286 [patent_doc_number] => 12620443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Semiconductor memory device with operation-specific pass voltages [patent_app_type] => utility [patent_app_number] => 18/446106 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 18867 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446106
Semiconductor memory device with operation-specific pass voltages Aug 7, 2023 Issued
Array ( [id] => 20507903 [patent_doc_number] => 12542185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Read power savings by temporarily disabling bitline voltage [patent_app_type] => utility [patent_app_number] => 18/229705 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 8219 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229705
Read power savings by temporarily disabling bitline voltage Aug 2, 2023 Issued
Array ( [id] => 19406884 [patent_doc_number] => 20240290395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => OPEN BLOCK READ ICC REDUCTION [patent_app_type] => utility [patent_app_number] => 18/360634 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360634
Open block read ICC reduction Jul 26, 2023 Issued
Array ( [id] => 19604452 [patent_doc_number] => 20240395332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => NON-VOLATILE MEMORY WITH SUB-BLOCK ERASE [patent_app_type] => utility [patent_app_number] => 18/359829 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359829
NON-VOLATILE MEMORY WITH SUB-BLOCK ERASE Jul 25, 2023 Abandoned
Array ( [id] => 19269051 [patent_doc_number] => 20240212755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => X-DIRECTION DIVIDED SUB-BLOCK MODE IN NAND [patent_app_type] => utility [patent_app_number] => 18/358654 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358654
X-direction divided sub-block mode in NAND Jul 24, 2023 Issued
Array ( [id] => 19237038 [patent_doc_number] => 20240194233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE INCLUDING MEMORY PACKAGE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/328781 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328781
MEMORY DEVICE INCLUDING MEMORY PACKAGE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE Jun 4, 2023 Issued
Array ( [id] => 18957753 [patent_doc_number] => 20240046080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => VERTICAL NAND FLASH TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/327732 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327732
VERTICAL NAND FLASH TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME May 31, 2023 Pending
Array ( [id] => 19237081 [patent_doc_number] => 20240194276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY CONTROL [patent_app_type] => utility [patent_app_number] => 18/326750 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326750
MEMORY CONTROL May 30, 2023 Pending
Array ( [id] => 19406877 [patent_doc_number] => 20240290388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORIES, STORAGE SYSTEMS AND ELECTRONIC PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/323921 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323921
Memory with separate drivers for word lines and select gates May 24, 2023 Issued
Array ( [id] => 20305206 [patent_doc_number] => 12451202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Memory device with sub-processor for parallel control of program voltage and pass/fail check and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/320200 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3644 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320200
Memory device with sub-processor for parallel control of program voltage and pass/fail check and method of operating the same May 18, 2023 Issued
Array ( [id] => 19145997 [patent_doc_number] => 20240145012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => STORAGE DEVICES AND OPERATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/320409 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320409
STORAGE DEVICES AND OPERATING METHODS THEREOF May 18, 2023 Pending
Array ( [id] => 20266824 [patent_doc_number] => 12437820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory including thermal anneal circuits and methods for operating the same [patent_app_type] => utility [patent_app_number] => 18/199308 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 10143 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199308
Memory including thermal anneal circuits and methods for operating the same May 17, 2023 Issued
Array ( [id] => 20266823 [patent_doc_number] => 12437819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory device with current measure for calculating inhibit cells [patent_app_type] => utility [patent_app_number] => 18/317670 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6519 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317670
Memory device with current measure for calculating inhibit cells May 14, 2023 Issued
Array ( [id] => 19483733 [patent_doc_number] => 20240331775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/307700 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307700
Memory device and operation method thereof Apr 25, 2023 Issued
Array ( [id] => 19347882 [patent_doc_number] => 20240256846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MULTIPLEXORS FOR NEURAL NETWORK ARRAY [patent_app_type] => utility [patent_app_number] => 18/135664 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135664
MULTIPLEXORS FOR NEURAL NETWORK ARRAY Apr 16, 2023 Pending
Array ( [id] => 18993031 [patent_doc_number] => 20240065000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/169436 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169436
Nonvolatile memory device and operating method of the same Feb 14, 2023 Issued
Array ( [id] => 20507893 [patent_doc_number] => 12542175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor device including pre-charge circuit and a method of operating thereof [patent_app_type] => utility [patent_app_number] => 18/169588 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 2225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169588
Semiconductor device including pre-charge circuit and a method of operating thereof Feb 14, 2023 Issued
Array ( [id] => 19384299 [patent_doc_number] => 20240274169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => OPERATION METHOD FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/168638 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168638 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168638
Operation method for memory device Feb 13, 2023 Issued
Array ( [id] => 19085925 [patent_doc_number] => 20240112726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SENSE AMPLIFIER AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/169100 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169100
Sense amplifier and operating method of the same Feb 13, 2023 Issued
Array ( [id] => 20243938 [patent_doc_number] => 12424268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory and operating method therefor [patent_app_type] => utility [patent_app_number] => 18/157059 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4532 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157059
Memory and operating method therefor Jan 18, 2023 Issued
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