Marie D. Bays

Array ( [id] => 20776964 [patent_doc_number] => 12660662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Methods and apparatus to adhere a dielectric to a nonconductive layer in circuit devices [patent_app_type] => utility [patent_app_number] => 17/855298 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6457 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20540567 [patent_doc_number] => 12557657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Electronic devices and methods of manufacturing electronic devices [patent_app_type] => utility [patent_app_number] => 17/853581 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 2218 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18112997 [patent_doc_number] => 20230005877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/809755 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17933371 [patent_doc_number] => 20220328497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/851675 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17949711 [patent_doc_number] => 20220336730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/850225 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18865992 [patent_doc_number] => 20230420429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => CHIP-ON-WAFER-ON-BOARD STRUCTURE USING SPACER DIE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/848448 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19392876 [patent_doc_number] => 20240282746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD FOR ESTABLISHING AN ELECTRIC CONNECTION TO AN ELECTRONIC COMPONENT AND A CHIP ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/569905 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18569905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18865942 [patent_doc_number] => 20230420379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/848059 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17919466 [patent_doc_number] => 20220321862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PIXEL STRUCTURE, IMAGE SENSOR DEVICE AND SYSTEM WITH PIXEL STRUCTURE, AND METHOD OF OPERATING THE PIXEL STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/847573 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20443249 [patent_doc_number] => 12514096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Backplane, backlight module and display panel [patent_app_type] => utility [patent_app_number] => 17/759392 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17759392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19409158 [patent_doc_number] => 20240292669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DISPLAY APPARATUS AND METHOD FOR MANUFACTURING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/569769 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 54155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18569769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848893 [patent_doc_number] => 20230411297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Active Silicon D2D Bridge [patent_app_type] => utility [patent_app_number] => 17/841188 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19213670 [patent_doc_number] => 12002742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/838412 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 8405 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17886573 [patent_doc_number] => 20220302051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/836117 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870832 [patent_doc_number] => 20220293569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS [patent_app_type] => utility [patent_app_number] => 17/832019 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18392733 [patent_doc_number] => 20230160953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS [patent_app_type] => utility [patent_app_number] => 17/832488 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18823075 [patent_doc_number] => 20230397416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Metal Hardmasks [patent_app_type] => utility [patent_app_number] => 17/831695 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20204152 [patent_doc_number] => 12406936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor package with substrate recess and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/829552 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 8816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18812737 [patent_doc_number] => 20230387074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => INTEGRATED CIRCUIT ASSEMBLIES HAVING INTERCONNECTION BRIDGES SPANNING RETICLE BOUNDARY / DICING STREETS OF MONOLITHIC STRUCTURES THEREIN [patent_app_type] => utility [patent_app_number] => 17/825350 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19341426 [patent_doc_number] => 12051621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Microelectronic assembly from processed substrate [patent_app_type] => utility [patent_app_number] => 17/825405 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6231 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825405 [rel_patent_id] =>[rel_patent_doc_number] =>)