Search

Marie D. Bays

Examiner (ID: 15536, Phone: (571)272-4559 , Office: P/3765 )

Most Active Art Unit
3728
Art Unit(s)
3728, 3765, 3732, 3208, 2404
Total Applications
3864
Issued Applications
2754
Pending Applications
238
Abandoned Applications
904

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16765573 [patent_doc_number] => 20210111155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MICROELECTRONIC ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/129095 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129095
Microelectronic assemblies Dec 20, 2020 Issued
Array ( [id] => 18277077 [patent_doc_number] => 11616025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Selective EMI shielding using preformed mask with fang design [patent_app_type] => utility [patent_app_number] => 17/126621 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 6206 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126621
Selective EMI shielding using preformed mask with fang design Dec 17, 2020 Issued
Array ( [id] => 19553889 [patent_doc_number] => 12137612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Organic photodetector [patent_app_type] => utility [patent_app_number] => 17/122797 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8530 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122797
Organic photodetector Dec 14, 2020 Issued
Array ( [id] => 18304601 [patent_doc_number] => 11626518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => FinFET device and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/121186 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 11448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121186
FinFET device and methods of forming the same Dec 13, 2020 Issued
Array ( [id] => 18032028 [patent_doc_number] => 11515226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Semiconductor package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/117588 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117588
Semiconductor package and method of fabricating the same Dec 9, 2020 Issued
Array ( [id] => 16781740 [patent_doc_number] => 20210118819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MITIGATING MOISTURE-DRIVEN DEGRADATION OF FEATURES DESIGNED TO PREVENT STRUCTURAL FAILURE OF SEMICONDUCTOR WAFERS [patent_app_type] => utility [patent_app_number] => 17/113032 [patent_app_country] => US [patent_app_date] => 2020-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113032
Mitigating moisture-driven degradation of features designed to prevent structural failure of semiconductor wafers Dec 4, 2020 Issued
Array ( [id] => 18104547 [patent_doc_number] => 11544437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => System for designing integrated circuit layout and method of making the integrated circuit layout [patent_app_type] => utility [patent_app_number] => 17/109820 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109820
System for designing integrated circuit layout and method of making the integrated circuit layout Dec 1, 2020 Issued
Array ( [id] => 17825923 [patent_doc_number] => 11430879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy [patent_app_type] => utility [patent_app_number] => 17/102098 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6296 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102098
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy Nov 22, 2020 Issued
Array ( [id] => 17630690 [patent_doc_number] => 20220165705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => MICROELECTRONICS PACKAGE WITH ENHANCED THERMAL DISSIPATION [patent_app_type] => utility [patent_app_number] => 16/953988 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953988
Microelectronics package with enhanced thermal dissipation Nov 19, 2020 Issued
Array ( [id] => 16660574 [patent_doc_number] => 20210057211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Epitaxies of a Chemical Compound Semiconductor [patent_app_type] => utility [patent_app_number] => 17/093865 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093865
Epitaxies of a chemical compound semiconductor Nov 9, 2020 Issued
Array ( [id] => 16660507 [patent_doc_number] => 20210057144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => InFO Coil on Metal Plate with Slot [patent_app_type] => utility [patent_app_number] => 17/092887 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092887
InFO coil on metal plate with slot Nov 8, 2020 Issued
Array ( [id] => 18172573 [patent_doc_number] => 11572269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor package using a polymer substrate [patent_app_type] => utility [patent_app_number] => 17/086633 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086633
Semiconductor package using a polymer substrate Nov 1, 2020 Issued
Array ( [id] => 16692280 [patent_doc_number] => 20210074759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSOR AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 17/081609 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081609
Complementary metal-oxide-semiconductor image sensor and method of making Oct 26, 2020 Issued
Array ( [id] => 17893261 [patent_doc_number] => 11456243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Semiconductor package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/080859 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3695 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080859
Semiconductor package structure and manufacturing method thereof Oct 26, 2020 Issued
Array ( [id] => 16724050 [patent_doc_number] => 20210091197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY CELLS HAVING ELECTRICALLY CONDUCTIVE NANODOTS AND APPARATUS HAVING SUCH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/080013 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080013
Memory cells having electrically conductive nanodots and apparatus having such memory cells Oct 25, 2020 Issued
Array ( [id] => 16624967 [patent_doc_number] => 20210043620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SEMICONDUCTOR DEVICE HAVING VOLTAGE REGULATORS EMBEDDED IN LAYERED PACKAGE [patent_app_type] => utility [patent_app_number] => 17/069517 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069517
Semiconductor device having voltage regulators embedded in layered package Oct 12, 2020 Issued
Array ( [id] => 17536688 [patent_doc_number] => 20220115297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TRANSISTOR WITH FLIP-CHIP TOPOLOGY AND POWER AMPLIFIER CONTAINING SAME [patent_app_type] => utility [patent_app_number] => 17/068051 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068051
Transistor with flip-chip topology and power amplifier containing same Oct 11, 2020 Issued
Array ( [id] => 16617326 [patent_doc_number] => 20210035979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => GATE NOBLE METAL NANOPARTICLES [patent_app_type] => utility [patent_app_number] => 17/065711 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065711
Gate noble metal nanoparticles Oct 7, 2020 Issued
Array ( [id] => 18016327 [patent_doc_number] => 11508634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Semiconductor package structure, electronic device, and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/063571 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 11051 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063571
Semiconductor package structure, electronic device, and method for manufacturing the same Oct 4, 2020 Issued
Array ( [id] => 18137241 [patent_doc_number] => 11562930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/061200 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061200
Semiconductor structure Sep 30, 2020 Issued
Menu