Search

Marie D. Bays

Examiner (ID: 15536, Phone: (571)272-4559 , Office: P/3765 )

Most Active Art Unit
3728
Art Unit(s)
3728, 3765, 3732, 3208, 2404
Total Applications
3864
Issued Applications
2754
Pending Applications
238
Abandoned Applications
904

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18379783 [patent_doc_number] => 20230154872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/097847 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097847
Electronic package and manufacturing method thereof Jan 16, 2023 Issued
Array ( [id] => 18898704 [patent_doc_number] => 20240014189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/154739 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154739
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD Jan 12, 2023 Pending
Array ( [id] => 19023185 [patent_doc_number] => 20240079356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Integrated Circuit Packages and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/151623 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151623
Integrated Circuit Packages and Methods of Forming the Same Jan 8, 2023 Pending
Array ( [id] => 18456480 [patent_doc_number] => 20230197762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSOR AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 18/151917 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151917
Complementary metal-oxide-semiconductor image sensor and method of making Jan 8, 2023 Issued
Array ( [id] => 19255196 [patent_doc_number] => 20240206193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS [patent_app_type] => utility [patent_app_number] => 18/151742 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151742
STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS Jan 8, 2023 Pending
Array ( [id] => 20598234 [patent_doc_number] => 12581974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Semiconductor device and method of making a semiconductor package with graphene-coated interconnects [patent_app_type] => utility [patent_app_number] => 18/150634 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150634
Semiconductor device and method of making a semiconductor package with graphene-coated interconnects Jan 4, 2023 Issued
Array ( [id] => 18959182 [patent_doc_number] => 20240047509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Packages with Chips Comprising Inductor-Vias and Methods Forming the Same [patent_app_type] => utility [patent_app_number] => 18/150624 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150624 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150624
Packages with Chips Comprising Inductor-Vias and Methods Forming the Same Jan 4, 2023 Pending
Array ( [id] => 18363472 [patent_doc_number] => 20230145063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => Process Control for Package Formation [patent_app_type] => utility [patent_app_number] => 18/149472 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149472
Process control for package formation Jan 2, 2023 Issued
Array ( [id] => 18362590 [patent_doc_number] => 20230144181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => CERAMIC LAMINATED SUBSTRATE, MODULE, AND METHOD OF MANUFACTURING CERAMIC LAMINATED SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/149205 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149205
Ceramic laminated substrate, module, and method of manufacturing ceramic laminated substrate Jan 2, 2023 Issued
Array ( [id] => 19161177 [patent_doc_number] => 20240153884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/148440 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148440
Electronic package and manufacturing method thereof Dec 29, 2022 Issued
Array ( [id] => 18345125 [patent_doc_number] => 20230133235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MICROELECTRONIC ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 18/090801 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090801
Microelectronic assemblies Dec 28, 2022 Issued
Array ( [id] => 18473195 [patent_doc_number] => 20230207483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => ISOLATED TRANSFORMER WITH INTEGRATED SHIELD TOPOLOGY FOR REDUCED EMI [patent_app_type] => utility [patent_app_number] => 18/086610 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 1 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086610
Isolated transformer with integrated shield topology for reduced EMI Dec 20, 2022 Issued
Array ( [id] => 20692097 [patent_doc_number] => 12622273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Fan-out type semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/085859 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1056 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085859
Fan-out type semiconductor package and method of manufacturing the same Dec 20, 2022 Issued
Array ( [id] => 20598216 [patent_doc_number] => 12581956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Through molding contact enabled EMI shielding [patent_app_type] => utility [patent_app_number] => 18/067565 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 3430 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067565 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067565
Through molding contact enabled EMI shielding Dec 15, 2022 Issued
Array ( [id] => 20720087 [patent_doc_number] => 12635359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Array substrate and display panel [patent_app_type] => utility [patent_app_number] => 18/067494 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067494 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067494
Array substrate and display panel Dec 15, 2022 Issued
Array ( [id] => 19252806 [patent_doc_number] => 20240203803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/082012 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082012
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES Dec 14, 2022 Pending
Array ( [id] => 19252941 [patent_doc_number] => 20240203938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED BARE DIE PACKAGE, AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 18/066448 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066448
Integrated bare die package, and related fabrication methods Dec 14, 2022 Issued
Array ( [id] => 18456295 [patent_doc_number] => 20230197577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => Semiconductor Devices Including a Premolded Leadframe and a Semiconductor Package [patent_app_type] => utility [patent_app_number] => 18/082238 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082238
Semiconductor Devices Including a Premolded Leadframe and a Semiconductor Package Dec 14, 2022 Pending
Array ( [id] => 19252971 [patent_doc_number] => 20240203968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE [patent_app_type] => utility [patent_app_number] => 18/081461 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081461
CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE Dec 13, 2022 Pending
Array ( [id] => 19596020 [patent_doc_number] => 12153868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Integrated circuit having non-integral multiple pitch [patent_app_type] => utility [patent_app_number] => 18/064027 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064027 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064027
Integrated circuit having non-integral multiple pitch Dec 8, 2022 Issued
Menu