Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6986855
[patent_doc_number] => 20010036687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Substrateless chip scale package and method of making same'
[patent_app_type] => new
[patent_app_number] => 09/892151
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2245
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20010036687.pdf
[firstpage_image] =>[orig_patent_app_number] => 09892151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/892151 | Substrateless chip scale package and method of making same | Jun 25, 2001 | Issued |
Array
(
[id] => 1474436
[patent_doc_number] => 06387742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-14
[patent_title] => 'Thermal conductivity enhanced semiconductor structures and fabrication processes'
[patent_app_type] => B2
[patent_app_number] => 09/862451
[patent_app_country] => US
[patent_app_date] => 2001-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 24
[patent_no_of_words] => 4503
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/387/06387742.pdf
[firstpage_image] =>[orig_patent_app_number] => 09862451
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/862451 | Thermal conductivity enhanced semiconductor structures and fabrication processes | May 22, 2001 | Issued |
Array
(
[id] => 6947925
[patent_doc_number] => 20010021559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-13
[patent_title] => 'Integrated circuit, components thereof and manufacturing method'
[patent_app_type] => new
[patent_app_number] => 09/853632
[patent_app_country] => US
[patent_app_date] => 2001-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5216
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 28
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20010021559.pdf
[firstpage_image] =>[orig_patent_app_number] => 09853632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/853632 | Integrated circuit, components thereof and manufacturing method | May 13, 2001 | Issued |
Array
(
[id] => 6896190
[patent_doc_number] => 20010026980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-04
[patent_title] => 'Semiconductor device and a method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/835341
[patent_app_country] => US
[patent_app_date] => 2001-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 12222
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20010026980.pdf
[firstpage_image] =>[orig_patent_app_number] => 09835341
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/835341 | Semiconductor device and a method of manufacturing the same | Apr 16, 2001 | Issued |
Array
(
[id] => 7078477
[patent_doc_number] => 20010041384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'Method of producing semiconductor device and configuration thereof, and lead frame used in said method'
[patent_app_type] => new
[patent_app_number] => 09/828132
[patent_app_country] => US
[patent_app_date] => 2001-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6722
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20010041384.pdf
[firstpage_image] =>[orig_patent_app_number] => 09828132
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/828132 | Method of producing semiconductor device and configuration thereof, and lead frame used in said method | Apr 8, 2001 | Issued |
Array
(
[id] => 1485110
[patent_doc_number] => 06365435
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Method for producing a flip chip package'
[patent_app_type] => B1
[patent_app_number] => 09/815241
[patent_app_country] => US
[patent_app_date] => 2001-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2634
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/365/06365435.pdf
[firstpage_image] =>[orig_patent_app_number] => 09815241
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/815241 | Method for producing a flip chip package | Mar 21, 2001 | Issued |
Array
(
[id] => 6908179
[patent_doc_number] => 20010010946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'IC die power connection using canted coil spring'
[patent_app_type] => new
[patent_app_number] => 09/813761
[patent_app_country] => US
[patent_app_date] => 2001-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6088
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20010010946.pdf
[firstpage_image] =>[orig_patent_app_number] => 09813761
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/813761 | IC die power connection using canted coil spring | Mar 20, 2001 | Issued |
Array
(
[id] => 1553458
[patent_doc_number] => 06348371
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Method of forming self-aligned twin wells'
[patent_app_type] => B1
[patent_app_number] => 09/809831
[patent_app_country] => US
[patent_app_date] => 2001-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1629
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/348/06348371.pdf
[firstpage_image] =>[orig_patent_app_number] => 09809831
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/809831 | Method of forming self-aligned twin wells | Mar 18, 2001 | Issued |
Array
(
[id] => 7640335
[patent_doc_number] => 06395579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-28
[patent_title] => 'Controlling packaging encapsulant leakage'
[patent_app_type] => B2
[patent_app_number] => 09/789892
[patent_app_country] => US
[patent_app_date] => 2001-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1397
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 9
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/395/06395579.pdf
[firstpage_image] =>[orig_patent_app_number] => 09789892
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/789892 | Controlling packaging encapsulant leakage | Feb 20, 2001 | Issued |
Array
(
[id] => 1435857
[patent_doc_number] => 06355500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-03-12
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/768451
[patent_app_country] => US
[patent_app_date] => 2001-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 81
[patent_no_of_words] => 20186
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/355/06355500.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768451
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768451 | Semiconductor device and manufacturing method thereof | Jan 24, 2001 | Issued |
Array
(
[id] => 6878175
[patent_doc_number] => 20010002330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-31
[patent_title] => 'Rolling ball connector'
[patent_app_type] => new-utility
[patent_app_number] => 09/768112
[patent_app_country] => US
[patent_app_date] => 2001-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3361
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20010002330.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768112 | Rolling ball connector | Jan 22, 2001 | Issued |
Array
(
[id] => 1462389
[patent_doc_number] => 06350625
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Optoelectronic packaging submount arrangement providing 90 degree electrical conductor turns and method of forming thereof'
[patent_app_type] => B1
[patent_app_number] => 09/753272
[patent_app_country] => US
[patent_app_date] => 2000-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 3408
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350625.pdf
[firstpage_image] =>[orig_patent_app_number] => 09753272
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/753272 | Optoelectronic packaging submount arrangement providing 90 degree electrical conductor turns and method of forming thereof | Dec 27, 2000 | Issued |
Array
(
[id] => 1585347
[patent_doc_number] => 06358773
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method of making substrate for use in forming image sensor package'
[patent_app_type] => B1
[patent_app_number] => 09/748231
[patent_app_country] => US
[patent_app_date] => 2000-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2541
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/358/06358773.pdf
[firstpage_image] =>[orig_patent_app_number] => 09748231
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/748231 | Method of making substrate for use in forming image sensor package | Dec 26, 2000 | Issued |
Array
(
[id] => 1594267
[patent_doc_number] => 06383844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-07
[patent_title] => 'Multi-chip bonding method and apparatus'
[patent_app_type] => B2
[patent_app_number] => 09/748812
[patent_app_country] => US
[patent_app_date] => 2000-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 6542
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 325
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/383/06383844.pdf
[firstpage_image] =>[orig_patent_app_number] => 09748812
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/748812 | Multi-chip bonding method and apparatus | Dec 25, 2000 | Issued |
Array
(
[id] => 1494154
[patent_doc_number] => 06342406
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-29
[patent_title] => 'Flip chip on glass image sensor package fabrication method'
[patent_app_type] => B1
[patent_app_number] => 09/714682
[patent_app_country] => US
[patent_app_date] => 2000-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 6925
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/342/06342406.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714682 | Flip chip on glass image sensor package fabrication method | Nov 14, 2000 | Issued |
Array
(
[id] => 4381071
[patent_doc_number] => 06294419
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Structure and method for improved latch-up using dual depth STI with impurity implant'
[patent_app_type] => 1
[patent_app_number] => 9/705882
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 4170
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294419.pdf
[firstpage_image] =>[orig_patent_app_number] => 705882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705882 | Structure and method for improved latch-up using dual depth STI with impurity implant | Nov 5, 2000 | Issued |
Array
(
[id] => 4321853
[patent_doc_number] => 06331469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-18
[patent_title] => 'Trench isolation structure, semiconductor device having the same, and trench isolation method'
[patent_app_type] => 1
[patent_app_number] => 9/684822
[patent_app_country] => US
[patent_app_date] => 2000-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 5047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/331/06331469.pdf
[firstpage_image] =>[orig_patent_app_number] => 684822
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/684822 | Trench isolation structure, semiconductor device having the same, and trench isolation method | Oct 9, 2000 | Issued |
Array
(
[id] => 4350364
[patent_doc_number] => 06291300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Manufacturing method of semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/661442
[patent_app_country] => US
[patent_app_date] => 2000-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3639
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/291/06291300.pdf
[firstpage_image] =>[orig_patent_app_number] => 661442
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/661442 | Manufacturing method of semiconductor devices | Sep 12, 2000 | Issued |
Array
(
[id] => 1585457
[patent_doc_number] => 06358801
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination'
[patent_app_type] => B1
[patent_app_number] => 09/644282
[patent_app_country] => US
[patent_app_date] => 2000-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2407
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/358/06358801.pdf
[firstpage_image] =>[orig_patent_app_number] => 09644282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644282 | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination | Aug 21, 2000 | Issued |
Array
(
[id] => 1433317
[patent_doc_number] => 06340607
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Process for mounting semiconductor device and mounting apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/631282
[patent_app_country] => US
[patent_app_date] => 2000-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 5678
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340607.pdf
[firstpage_image] =>[orig_patent_app_number] => 09631282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/631282 | Process for mounting semiconductor device and mounting apparatus | Aug 2, 2000 | Issued |