Marina Annette Tietjen

Array ( [id] => 4145295 [patent_doc_number] => 06063647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method for making circuit elements for a z-axis interconnect' [patent_app_type] => 1 [patent_app_number] => 8/986882 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063647.pdf [firstpage_image] =>[orig_patent_app_number] => 986882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943068 [patent_doc_number] => 05976900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of reducing impurity contamination in semiconductor process chambers' [patent_app_type] => 1 [patent_app_number] => 8/986371 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976900.pdf [firstpage_image] =>[orig_patent_app_number] => 986371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4245836 [patent_doc_number] => 06136654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming thin silicon nitride or silicon oxynitride gate dielectrics' [patent_app_type] => 1 [patent_app_number] => 8/984967 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2944 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136654.pdf [firstpage_image] =>[orig_patent_app_number] => 984967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037762 [patent_doc_number] => 05908308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array' [patent_app_type] => 1 [patent_app_number] => 8/980883 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908308.pdf [firstpage_image] =>[orig_patent_app_number] => 980883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113695 [patent_doc_number] => 06046071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Plastic molded semiconductor package and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/976603 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 12021 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046071.pdf [firstpage_image] =>[orig_patent_app_number] => 976603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3938230 [patent_doc_number] => 05981403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Layered silicon nitride deposition process' [patent_app_type] => 1 [patent_app_number] => 8/977319 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1318 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981403.pdf [firstpage_image] =>[orig_patent_app_number] => 977319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805917 [patent_doc_number] => 05854093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Direct attachment of silicon chip to circuit carrier' [patent_app_type] => 1 [patent_app_number] => 8/976685 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2236 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854093.pdf [firstpage_image] =>[orig_patent_app_number] => 976685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185162 [patent_doc_number] => 06093576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Semiconductor sensor and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/974499 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7324 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093576.pdf [firstpage_image] =>[orig_patent_app_number] => 974499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4046162 [patent_doc_number] => 05869353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Modular panel stacking process' [patent_app_type] => 1 [patent_app_number] => 8/971499 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5793 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869353.pdf [firstpage_image] =>[orig_patent_app_number] => 971499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805899 [patent_doc_number] => 05854092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method for spray-cooling a tunable semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/968000 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2707 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854092.pdf [firstpage_image] =>[orig_patent_app_number] => 968000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867166 [patent_doc_number] => 05837558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Integrated circuit chip packaging method' [patent_app_type] => 1 [patent_app_number] => 8/963799 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2097 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837558.pdf [firstpage_image] =>[orig_patent_app_number] => 963799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3926135 [patent_doc_number] => 05877066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Narrow width trenches for field isolation in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/964431 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 2067 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877066.pdf [firstpage_image] =>[orig_patent_app_number] => 964431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3941224 [patent_doc_number] => 05989935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Column grid array for semiconductor packaging and method' [patent_app_type] => 1 [patent_app_number] => 8/961783 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1928 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989935.pdf [firstpage_image] =>[orig_patent_app_number] => 961783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3990749 [patent_doc_number] => 05891758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/962395 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 9185 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891758.pdf [firstpage_image] =>[orig_patent_app_number] => 962395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994313 [patent_doc_number] => 05918131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method of manufacturing a shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 8/961062 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1908 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918131.pdf [firstpage_image] =>[orig_patent_app_number] => 961062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4039372 [patent_doc_number] => 05926740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Graded anti-reflective coating for IC lithography' [patent_app_type] => 1 [patent_app_number] => 8/958023 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5877 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926740.pdf [firstpage_image] =>[orig_patent_app_number] => 958023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4233327 [patent_doc_number] => 06117764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Use of a plasma source to form a layer during the formation of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/046835 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2446 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117764.pdf [firstpage_image] =>[orig_patent_app_number] => 046835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4246480 [patent_doc_number] => 06221689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method for improving the reliability of underfill process for a chip' [patent_app_type] => 1 [patent_app_number] => 8/957449 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1978 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221689.pdf [firstpage_image] =>[orig_patent_app_number] => 957449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944452 [patent_doc_number] => 05998282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment' [patent_app_type] => 1 [patent_app_number] => 8/955162 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1447 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998282.pdf [firstpage_image] =>[orig_patent_app_number] => 955162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4218642 [patent_doc_number] => 06040203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Clock skew minimization and method for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/954709 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3159 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040203.pdf [firstpage_image] =>[orig_patent_app_number] => 954709 [rel_patent_id] =>[rel_patent_doc_number] =>)