Search

Marina Annette Tietjen

Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3799
Total Applications
1026
Issued Applications
731
Pending Applications
46
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4050184 [patent_doc_number] => 05943555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Micro mechanical component and production process thereof' [patent_app_type] => 1 [patent_app_number] => 8/954307 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 11627 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943555.pdf [firstpage_image] =>[orig_patent_app_number] => 954307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954307
Micro mechanical component and production process thereof Oct 16, 1997 Issued
Array ( [id] => 3889045 [patent_doc_number] => 05834346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure' [patent_app_type] => 1 [patent_app_number] => 8/949351 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2306 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834346.pdf [firstpage_image] =>[orig_patent_app_number] => 949351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949351
Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure Oct 13, 1997 Issued
Array ( [id] => 4056974 [patent_doc_number] => 05895230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Integrated circuit chip package having configurable contacts and method for making the same' [patent_app_type] => 1 [patent_app_number] => 8/949097 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895230.pdf [firstpage_image] =>[orig_patent_app_number] => 949097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949097
Integrated circuit chip package having configurable contacts and method for making the same Oct 9, 1997 Issued
Array ( [id] => 3968902 [patent_doc_number] => 05904523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Process for device fabrication in which a layer of oxynitride is formed at low temperatures' [patent_app_type] => 1 [patent_app_number] => 8/943585 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3943 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904523.pdf [firstpage_image] =>[orig_patent_app_number] => 943585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943585
Process for device fabrication in which a layer of oxynitride is formed at low temperatures Oct 2, 1997 Issued
Array ( [id] => 4004575 [patent_doc_number] => 05960310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Polishing methods for forming a contact plug' [patent_app_type] => 1 [patent_app_number] => 8/942859 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4258 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960310.pdf [firstpage_image] =>[orig_patent_app_number] => 942859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942859
Polishing methods for forming a contact plug Oct 1, 1997 Issued
Array ( [id] => 4046377 [patent_doc_number] => 05869365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method of forming T electrode in field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/942821 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869365.pdf [firstpage_image] =>[orig_patent_app_number] => 942821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942821
Method of forming T electrode in field effect transistor Oct 1, 1997 Issued
Array ( [id] => 3806544 [patent_doc_number] => 05854141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Inorganic seal for encapsulation of an organic layer and method for making the same' [patent_app_type] => 1 [patent_app_number] => 8/941447 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1800 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854141.pdf [firstpage_image] =>[orig_patent_app_number] => 941447 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941447
Inorganic seal for encapsulation of an organic layer and method for making the same Sep 29, 1997 Issued
Array ( [id] => 4012475 [patent_doc_number] => 05880007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Planarization of a non-conformal device layer in semiconductor fabrication' [patent_app_type] => 1 [patent_app_number] => 8/940650 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2618 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880007.pdf [firstpage_image] =>[orig_patent_app_number] => 940650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940650
Planarization of a non-conformal device layer in semiconductor fabrication Sep 29, 1997 Issued
Array ( [id] => 4030588 [patent_doc_number] => 05963781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Technique for determining semiconductor substrate thickness' [patent_app_type] => 1 [patent_app_number] => 8/941799 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963781.pdf [firstpage_image] =>[orig_patent_app_number] => 941799 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941799
Technique for determining semiconductor substrate thickness Sep 29, 1997 Issued
Array ( [id] => 4056805 [patent_doc_number] => 05863816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Fabrication method for chip size semiconductor package' [patent_app_type] => 1 [patent_app_number] => 8/937511 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/863/05863816.pdf [firstpage_image] =>[orig_patent_app_number] => 937511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937511
Fabrication method for chip size semiconductor package Sep 24, 1997 Issued
Array ( [id] => 4003859 [patent_doc_number] => 05960259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Optical apparatus and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/937131 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 61 [patent_no_of_words] => 28311 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960259.pdf [firstpage_image] =>[orig_patent_app_number] => 937131 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937131
Optical apparatus and method for producing the same Sep 23, 1997 Issued
Array ( [id] => 4233512 [patent_doc_number] => 06074895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of forming a flip chip assembly' [patent_app_type] => 1 [patent_app_number] => 8/936032 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3686 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074895.pdf [firstpage_image] =>[orig_patent_app_number] => 936032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936032
Method of forming a flip chip assembly Sep 22, 1997 Issued
Array ( [id] => 3934657 [patent_doc_number] => 05972734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Interposer for ball grid array (BGA) package' [patent_app_type] => 1 [patent_app_number] => 8/932711 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972734.pdf [firstpage_image] =>[orig_patent_app_number] => 932711 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932711
Interposer for ball grid array (BGA) package Sep 16, 1997 Issued
Array ( [id] => 4097472 [patent_doc_number] => 06048744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Integrated circuit package alignment feature' [patent_app_type] => 1 [patent_app_number] => 8/929843 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3665 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048744.pdf [firstpage_image] =>[orig_patent_app_number] => 929843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929843
Integrated circuit package alignment feature Sep 14, 1997 Issued
Array ( [id] => 3957178 [patent_doc_number] => 05930620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures' [patent_app_type] => 1 [patent_app_number] => 8/928619 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930620.pdf [firstpage_image] =>[orig_patent_app_number] => 928619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928619
Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures Sep 11, 1997 Issued
Array ( [id] => 3935046 [patent_doc_number] => 05972760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method of manufacturing a semiconductor device containing shallow LDD junctions' [patent_app_type] => 1 [patent_app_number] => 8/924639 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2885 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972760.pdf [firstpage_image] =>[orig_patent_app_number] => 924639 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924639
Method of manufacturing a semiconductor device containing shallow LDD junctions Sep 4, 1997 Issued
Array ( [id] => 4197585 [patent_doc_number] => 06013556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method of integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 8/924728 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 684 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013556.pdf [firstpage_image] =>[orig_patent_app_number] => 924728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924728
Method of integrated circuit fabrication Sep 4, 1997 Issued
Array ( [id] => 3953045 [patent_doc_number] => 05940715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/920903 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 9403 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940715.pdf [firstpage_image] =>[orig_patent_app_number] => 920903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920903
Method for manufacturing semiconductor device Aug 28, 1997 Issued
Array ( [id] => 4042052 [patent_doc_number] => 05874323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method of providing electrical contact to component leads' [patent_app_type] => 1 [patent_app_number] => 8/919536 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 4875 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874323.pdf [firstpage_image] =>[orig_patent_app_number] => 919536 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919536
Method of providing electrical contact to component leads Aug 27, 1997 Issued
Array ( [id] => 3759700 [patent_doc_number] => 05843826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Deep submicron MOSFET device' [patent_app_type] => 1 [patent_app_number] => 8/924431 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3311 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843826.pdf [firstpage_image] =>[orig_patent_app_number] => 924431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924431
Deep submicron MOSFET device Aug 26, 1997 Issued
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