Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4050184
[patent_doc_number] => 05943555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Micro mechanical component and production process thereof'
[patent_app_type] => 1
[patent_app_number] => 8/954307
[patent_app_country] => US
[patent_app_date] => 1997-10-17
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[pdf_file] => patents/05/943/05943555.pdf
[firstpage_image] =>[orig_patent_app_number] => 954307
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/954307 | Micro mechanical component and production process thereof | Oct 16, 1997 | Issued |
Array
(
[id] => 3889045
[patent_doc_number] => 05834346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure'
[patent_app_type] => 1
[patent_app_number] => 8/949351
[patent_app_country] => US
[patent_app_date] => 1997-10-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/949351 | Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure | Oct 13, 1997 | Issued |
Array
(
[id] => 4056974
[patent_doc_number] => 05895230
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Integrated circuit chip package having configurable contacts and method for making the same'
[patent_app_type] => 1
[patent_app_number] => 8/949097
[patent_app_country] => US
[patent_app_date] => 1997-10-10
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[pdf_file] => patents/05/895/05895230.pdf
[firstpage_image] =>[orig_patent_app_number] => 949097
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/949097 | Integrated circuit chip package having configurable contacts and method for making the same | Oct 9, 1997 | Issued |
Array
(
[id] => 3968902
[patent_doc_number] => 05904523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Process for device fabrication in which a layer of oxynitride is formed at low temperatures'
[patent_app_type] => 1
[patent_app_number] => 8/943585
[patent_app_country] => US
[patent_app_date] => 1997-10-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/943585 | Process for device fabrication in which a layer of oxynitride is formed at low temperatures | Oct 2, 1997 | Issued |
Array
(
[id] => 4004575
[patent_doc_number] => 05960310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Polishing methods for forming a contact plug'
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[patent_app_number] => 8/942859
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/942859 | Polishing methods for forming a contact plug | Oct 1, 1997 | Issued |
Array
(
[id] => 4046377
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[patent_issue_date] => 1999-02-09
[patent_title] => 'Method of forming T electrode in field effect transistor'
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[patent_app_number] => 8/942821
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[firstpage_image] =>[orig_patent_app_number] => 942821
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/942821 | Method of forming T electrode in field effect transistor | Oct 1, 1997 | Issued |
Array
(
[id] => 3806544
[patent_doc_number] => 05854141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'Inorganic seal for encapsulation of an organic layer and method for making the same'
[patent_app_type] => 1
[patent_app_number] => 8/941447
[patent_app_country] => US
[patent_app_date] => 1997-09-30
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[pdf_file] => patents/05/854/05854141.pdf
[firstpage_image] =>[orig_patent_app_number] => 941447
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941447 | Inorganic seal for encapsulation of an organic layer and method for making the same | Sep 29, 1997 | Issued |
Array
(
[id] => 4012475
[patent_doc_number] => 05880007
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Planarization of a non-conformal device layer in semiconductor fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/940650
[patent_app_country] => US
[patent_app_date] => 1997-09-30
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 940650
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/940650 | Planarization of a non-conformal device layer in semiconductor fabrication | Sep 29, 1997 | Issued |
Array
(
[id] => 4030588
[patent_doc_number] => 05963781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Technique for determining semiconductor substrate thickness'
[patent_app_type] => 1
[patent_app_number] => 8/941799
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[firstpage_image] =>[orig_patent_app_number] => 941799
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941799 | Technique for determining semiconductor substrate thickness | Sep 29, 1997 | Issued |
Array
(
[id] => 4056805
[patent_doc_number] => 05863816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Fabrication method for chip size semiconductor package'
[patent_app_type] => 1
[patent_app_number] => 8/937511
[patent_app_country] => US
[patent_app_date] => 1997-09-25
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[pdf_file] => patents/05/863/05863816.pdf
[firstpage_image] =>[orig_patent_app_number] => 937511
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937511 | Fabrication method for chip size semiconductor package | Sep 24, 1997 | Issued |
Array
(
[id] => 4003859
[patent_doc_number] => 05960259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Optical apparatus and method for producing the same'
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[patent_app_number] => 8/937131
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[pdf_file] => patents/05/960/05960259.pdf
[firstpage_image] =>[orig_patent_app_number] => 937131
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937131 | Optical apparatus and method for producing the same | Sep 23, 1997 | Issued |
Array
(
[id] => 4233512
[patent_doc_number] => 06074895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Method of forming a flip chip assembly'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/936032 | Method of forming a flip chip assembly | Sep 22, 1997 | Issued |
Array
(
[id] => 3934657
[patent_doc_number] => 05972734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Interposer for ball grid array (BGA) package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932711 | Interposer for ball grid array (BGA) package | Sep 16, 1997 | Issued |
Array
(
[id] => 4097472
[patent_doc_number] => 06048744
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[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Integrated circuit package alignment feature'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929843 | Integrated circuit package alignment feature | Sep 14, 1997 | Issued |
Array
(
[id] => 3957178
[patent_doc_number] => 05930620
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures'
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Array
(
[id] => 3935046
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Array
(
[id] => 4197585
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919536 | Method of providing electrical contact to component leads | Aug 27, 1997 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 924431
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924431 | Deep submicron MOSFET device | Aug 26, 1997 | Issued |