Search

Marina Annette Tietjen

Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3799
Total Applications
1026
Issued Applications
731
Pending Applications
46
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1564827 [patent_doc_number] => 06338980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method for manufacturing chip-scale package and manufacturing IC chip' [patent_app_type] => B1 [patent_app_number] => 09/630682 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 5912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338980.pdf [firstpage_image] =>[orig_patent_app_number] => 09630682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630682
Method for manufacturing chip-scale package and manufacturing IC chip Jul 31, 2000 Issued
Array ( [id] => 4349870 [patent_doc_number] => 06291264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Flip-chip package structure and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/629072 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291264.pdf [firstpage_image] =>[orig_patent_app_number] => 629072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629072
Flip-chip package structure and method of fabricating the same Jul 30, 2000 Issued
Array ( [id] => 1485148 [patent_doc_number] => 06365446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process' [patent_app_type] => B1 [patent_app_number] => 09/609751 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3173 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365446.pdf [firstpage_image] =>[orig_patent_app_number] => 09609751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609751
Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Jul 2, 2000 Issued
Array ( [id] => 1485107 [patent_doc_number] => 06365434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and apparatus for reduced flash encapsulation of microelectronic devices' [patent_app_type] => B1 [patent_app_number] => 09/605582 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5197 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365434.pdf [firstpage_image] =>[orig_patent_app_number] => 09605582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605582
Method and apparatus for reduced flash encapsulation of microelectronic devices Jun 27, 2000 Issued
Array ( [id] => 1459258 [patent_doc_number] => 06391686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Adhesive material applying method and apparatus, interconnect substrate, semiconductor device and manufacturing method thereof, circuit board and electronic instrument' [patent_app_type] => B1 [patent_app_number] => 09/592292 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 10015 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391686.pdf [firstpage_image] =>[orig_patent_app_number] => 09592292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592292
Adhesive material applying method and apparatus, interconnect substrate, semiconductor device and manufacturing method thereof, circuit board and electronic instrument Jun 11, 2000 Issued
Array ( [id] => 4335977 [patent_doc_number] => 06333207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Peelable lead structure and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/577474 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4695 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333207.pdf [firstpage_image] =>[orig_patent_app_number] => 577474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577474
Peelable lead structure and method of manufacture May 23, 2000 Issued
Array ( [id] => 4407877 [patent_doc_number] => 06300162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method of applying a protective layer to a microelectronic component' [patent_app_type] => 1 [patent_app_number] => 9/566523 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2531 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300162.pdf [firstpage_image] =>[orig_patent_app_number] => 566523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566523
Method of applying a protective layer to a microelectronic component May 7, 2000 Issued
Array ( [id] => 4312064 [patent_doc_number] => 06242284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for packaging a semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 9/565452 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2534 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242284.pdf [firstpage_image] =>[orig_patent_app_number] => 565452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565452
Method for packaging a semiconductor chip May 4, 2000 Issued
Array ( [id] => 4336381 [patent_doc_number] => 06333232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/549378 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 60 [patent_no_of_words] => 19773 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333232.pdf [firstpage_image] =>[orig_patent_app_number] => 549378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549378
Semiconductor device and method of manufacturing the same Apr 12, 2000 Issued
Array ( [id] => 1474531 [patent_doc_number] => 06387764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth' [patent_app_type] => B1 [patent_app_number] => 09/541395 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 41 [patent_no_of_words] => 8015 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387764.pdf [firstpage_image] =>[orig_patent_app_number] => 09541395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541395
Trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth Mar 30, 2000 Issued
Array ( [id] => 1535966 [patent_doc_number] => 06337225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method of making stacked die assemblies and modules' [patent_app_type] => B1 [patent_app_number] => 09/537732 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337225.pdf [firstpage_image] =>[orig_patent_app_number] => 09537732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537732
Method of making stacked die assemblies and modules Mar 29, 2000 Issued
Array ( [id] => 4406830 [patent_doc_number] => 06238950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated circuit with tightly coupled passive components' [patent_app_type] => 1 [patent_app_number] => 9/535972 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2317 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238950.pdf [firstpage_image] =>[orig_patent_app_number] => 535972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535972
Integrated circuit with tightly coupled passive components Mar 26, 2000 Issued
Array ( [id] => 4266364 [patent_doc_number] => 06306683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method of forming a flip chip assembly, and a flip chip assembly formed by the method' [patent_app_type] => 1 [patent_app_number] => 9/526569 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3684 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306683.pdf [firstpage_image] =>[orig_patent_app_number] => 526569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526569
Method of forming a flip chip assembly, and a flip chip assembly formed by the method Mar 15, 2000 Issued
Array ( [id] => 4343263 [patent_doc_number] => 06284554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Process for manufacturing a flip-chip integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/526042 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 5131 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284554.pdf [firstpage_image] =>[orig_patent_app_number] => 526042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526042
Process for manufacturing a flip-chip integrated circuit Mar 13, 2000 Issued
Array ( [id] => 1564929 [patent_doc_number] => 06339004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method of forming shallow trench isolation for preventing torn oxide' [patent_app_type] => B1 [patent_app_number] => 09/523372 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1703 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339004.pdf [firstpage_image] =>[orig_patent_app_number] => 09523372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523372
Method of forming shallow trench isolation for preventing torn oxide Mar 9, 2000 Issued
Array ( [id] => 1459405 [patent_doc_number] => 06391729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding' [patent_app_type] => B1 [patent_app_number] => 09/521342 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391729.pdf [firstpage_image] =>[orig_patent_app_number] => 09521342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521342
Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding Mar 8, 2000 Issued
Array ( [id] => 4358306 [patent_doc_number] => 06255176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of forming trench for semiconductor device isolation' [patent_app_type] => 1 [patent_app_number] => 9/517362 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2051 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255176.pdf [firstpage_image] =>[orig_patent_app_number] => 517362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517362
Method of forming trench for semiconductor device isolation Mar 1, 2000 Issued
Array ( [id] => 1446524 [patent_doc_number] => 06368893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/501262 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3347 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368893.pdf [firstpage_image] =>[orig_patent_app_number] => 09501262 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501262
Method of fabricating semiconductor device Feb 8, 2000 Issued
Array ( [id] => 1485101 [patent_doc_number] => 06365432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Fabrication process of semiconductor package and semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/487682 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 135 [patent_no_of_words] => 15578 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365432.pdf [firstpage_image] =>[orig_patent_app_number] => 09487682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487682
Fabrication process of semiconductor package and semiconductor package Jan 18, 2000 Issued
Array ( [id] => 4419858 [patent_doc_number] => 06225144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and machine for underfilling an assembly to form a semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/487042 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1790 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225144.pdf [firstpage_image] =>[orig_patent_app_number] => 487042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487042
Method and machine for underfilling an assembly to form a semiconductor package Jan 18, 2000 Issued
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