Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1564827
[patent_doc_number] => 06338980
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-15
[patent_title] => 'Method for manufacturing chip-scale package and manufacturing IC chip'
[patent_app_type] => B1
[patent_app_number] => 09/630682
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[pdf_file] => patents/06/338/06338980.pdf
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Array
(
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[patent_issue_date] => 2001-09-18
[patent_title] => 'Flip-chip package structure and method of fabricating the same'
[patent_app_type] => 1
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Array
(
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[patent_doc_number] => 06365446
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[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process'
[patent_app_type] => B1
[patent_app_number] => 09/609751
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/609751 | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process | Jul 2, 2000 | Issued |
Array
(
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[patent_doc_number] => 06365434
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[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Method and apparatus for reduced flash encapsulation of microelectronic devices'
[patent_app_type] => B1
[patent_app_number] => 09/605582
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[patent_app_date] => 2000-06-28
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Array
(
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[patent_issue_date] => 2002-05-21
[patent_title] => 'Adhesive material applying method and apparatus, interconnect substrate, semiconductor device and manufacturing method thereof, circuit board and electronic instrument'
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[patent_app_number] => 09/592292
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/592292 | Adhesive material applying method and apparatus, interconnect substrate, semiconductor device and manufacturing method thereof, circuit board and electronic instrument | Jun 11, 2000 | Issued |
Array
(
[id] => 4335977
[patent_doc_number] => 06333207
[patent_country] => US
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[patent_issue_date] => 2001-12-25
[patent_title] => 'Peelable lead structure and method of manufacture'
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Array
(
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[patent_title] => 'Method of applying a protective layer to a microelectronic component'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566523 | Method of applying a protective layer to a microelectronic component | May 7, 2000 | Issued |
Array
(
[id] => 4312064
[patent_doc_number] => 06242284
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[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for packaging a semiconductor chip'
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[patent_app_number] => 9/565452
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[firstpage_image] =>[orig_patent_app_number] => 565452
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/565452 | Method for packaging a semiconductor chip | May 4, 2000 | Issued |
Array
(
[id] => 4336381
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Array
(
[id] => 1474531
[patent_doc_number] => 06387764
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[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth'
[patent_app_type] => B1
[patent_app_number] => 09/541395
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Array
(
[id] => 1535966
[patent_doc_number] => 06337225
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[patent_title] => 'Method of making stacked die assemblies and modules'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/537732 | Method of making stacked die assemblies and modules | Mar 29, 2000 | Issued |
Array
(
[id] => 4406830
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Array
(
[id] => 4266364
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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