Search

Marina Annette Tietjen

Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3799
Total Applications
1026
Issued Applications
731
Pending Applications
46
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
09/482891 Semiconductor Device and Packaging Structure Thereof Jan 13, 2000 Abandoned
Array ( [id] => 1553419 [patent_doc_number] => 06348363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method for manufacturing a semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/483252 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5108 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348363.pdf [firstpage_image] =>[orig_patent_app_number] => 09483252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483252
Method for manufacturing a semiconductor package Jan 13, 2000 Issued
Array ( [id] => 4259089 [patent_doc_number] => 06258683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Local interconnection arrangement with reduced junction leakage and method of forming same' [patent_app_type] => 1 [patent_app_number] => 9/477741 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258683.pdf [firstpage_image] =>[orig_patent_app_number] => 477741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477741
Local interconnection arrangement with reduced junction leakage and method of forming same Jan 4, 2000 Issued
Array ( [id] => 4407898 [patent_doc_number] => 06309908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Package for an electronic component and a method of making it' [patent_app_type] => 1 [patent_app_number] => 9/469942 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2170 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309908.pdf [firstpage_image] =>[orig_patent_app_number] => 469942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469942
Package for an electronic component and a method of making it Dec 20, 1999 Issued
Array ( [id] => 4271150 [patent_doc_number] => 06323092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for forming a shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/466161 [patent_app_country] => US [patent_app_date] => 1999-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323092.pdf [firstpage_image] =>[orig_patent_app_number] => 466161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466161
Method for forming a shallow trench isolation Dec 17, 1999 Issued
Array ( [id] => 4301462 [patent_doc_number] => 06251703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'CMS coated microelectronic component and its method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/459272 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251703.pdf [firstpage_image] =>[orig_patent_app_number] => 459272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459272
CMS coated microelectronic component and its method of manufacture Dec 12, 1999 Issued
Array ( [id] => 4258412 [patent_doc_number] => 06258637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for thin film deposition on single-crystal semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 9/452922 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3237 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258637.pdf [firstpage_image] =>[orig_patent_app_number] => 452922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452922
Method for thin film deposition on single-crystal semiconductor substrates Dec 1, 1999 Issued
Array ( [id] => 4301928 [patent_doc_number] => 06251735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of forming shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/448018 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2035 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251735.pdf [firstpage_image] =>[orig_patent_app_number] => 448018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448018
Method of forming shallow trench isolation structure Nov 22, 1999 Issued
Array ( [id] => 4324353 [patent_doc_number] => 06329220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Packages for semiconductor die' [patent_app_type] => 1 [patent_app_number] => 9/448072 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3423 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329220.pdf [firstpage_image] =>[orig_patent_app_number] => 448072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448072
Packages for semiconductor die Nov 22, 1999 Issued
Array ( [id] => 4404329 [patent_doc_number] => 06271057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of making semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/443361 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271057.pdf [firstpage_image] =>[orig_patent_app_number] => 443361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443361
Method of making semiconductor chip package Nov 18, 1999 Issued
Array ( [id] => 4258994 [patent_doc_number] => 06258676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for forming a shallow trench isolation using HDP silicon oxynitride' [patent_app_type] => 1 [patent_app_number] => 9/431241 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2745 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258676.pdf [firstpage_image] =>[orig_patent_app_number] => 431241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431241
Method for forming a shallow trench isolation using HDP silicon oxynitride Oct 31, 1999 Issued
Array ( [id] => 1440954 [patent_doc_number] => 06335221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Ball grid array (BGA) encapsulation mold' [patent_app_type] => B1 [patent_app_number] => 09/430222 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3640 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335221.pdf [firstpage_image] =>[orig_patent_app_number] => 09430222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430222
Ball grid array (BGA) encapsulation mold Oct 28, 1999 Issued
Array ( [id] => 1550334 [patent_doc_number] => 06399449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor circuit using trench isolation and method of fabrication a trench isolator' [patent_app_type] => B1 [patent_app_number] => 09/425642 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2607 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399449.pdf [firstpage_image] =>[orig_patent_app_number] => 09425642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425642
Semiconductor circuit using trench isolation and method of fabrication a trench isolator Oct 21, 1999 Issued
Array ( [id] => 7640332 [patent_doc_number] => 06395582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Methods for forming ground vias in semiconductor packages' [patent_app_type] => B1 [patent_app_number] => 09/422212 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 10395 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395582.pdf [firstpage_image] =>[orig_patent_app_number] => 09422212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422212
Methods for forming ground vias in semiconductor packages Oct 18, 1999 Issued
Array ( [id] => 4368327 [patent_doc_number] => 06287890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Low cost decal material used for packaging' [patent_app_type] => 1 [patent_app_number] => 9/419512 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287890.pdf [firstpage_image] =>[orig_patent_app_number] => 419512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419512
Low cost decal material used for packaging Oct 17, 1999 Issued
Array ( [id] => 4294966 [patent_doc_number] => 06184154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method of processing the backside of a wafer within an epitaxial reactor chamber' [patent_app_type] => 1 [patent_app_number] => 9/417702 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6162 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184154.pdf [firstpage_image] =>[orig_patent_app_number] => 417702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417702
Method of processing the backside of a wafer within an epitaxial reactor chamber Oct 12, 1999 Issued
Array ( [id] => 4312036 [patent_doc_number] => 06242282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Circuit chip package and fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/411101 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242282.pdf [firstpage_image] =>[orig_patent_app_number] => 411101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411101
Circuit chip package and fabrication method Oct 3, 1999 Issued
Array ( [id] => 4406871 [patent_doc_number] => 06238954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'COF packaged semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/407801 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2630 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238954.pdf [firstpage_image] =>[orig_patent_app_number] => 407801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407801
COF packaged semiconductor Sep 27, 1999 Issued
Array ( [id] => 4408825 [patent_doc_number] => 06228727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method to form shallow trench isolations with rounded corners and reduced trench oxide recess' [patent_app_type] => 1 [patent_app_number] => 9/405061 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2714 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228727.pdf [firstpage_image] =>[orig_patent_app_number] => 405061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405061
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess Sep 26, 1999 Issued
Array ( [id] => 4376925 [patent_doc_number] => 06303400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Temporary attach article and method for temporary attach of devices to a substrate' [patent_app_type] => 1 [patent_app_number] => 9/404511 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2859 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303400.pdf [firstpage_image] =>[orig_patent_app_number] => 404511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404511
Temporary attach article and method for temporary attach of devices to a substrate Sep 22, 1999 Issued
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