Marina Annette Tietjen

Array ( [id] => 4343405 [patent_doc_number] => 06284564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'HDI chip attachment method for reduced processing' [patent_app_type] => 1 [patent_app_number] => 9/399461 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3362 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284564.pdf [firstpage_image] =>[orig_patent_app_number] => 399461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380652 [patent_doc_number] => 06277669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Wafer level packaging method and packages formed' [patent_app_type] => 1 [patent_app_number] => 9/396060 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5353 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277669.pdf [firstpage_image] =>[orig_patent_app_number] => 396060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4356752 [patent_doc_number] => 06190941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method of fabricating a circuit arrangement with thermal vias' [patent_app_type] => 1 [patent_app_number] => 9/396661 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2827 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190941.pdf [firstpage_image] =>[orig_patent_app_number] => 396661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4274795 [patent_doc_number] => 06281039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Hybrid device and a method of producing electrically active components by an assembly operation' [patent_app_type] => 1 [patent_app_number] => 9/394050 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281039.pdf [firstpage_image] =>[orig_patent_app_number] => 394050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309763 [patent_doc_number] => 06316285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Passivation layer for packaged integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/392201 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2935 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316285.pdf [firstpage_image] =>[orig_patent_app_number] => 392201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4285576 [patent_doc_number] => 06210992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Controlling packaging encapsulant leakage' [patent_app_type] => 1 [patent_app_number] => 9/386971 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/210/06210992.pdf [firstpage_image] =>[orig_patent_app_number] => 386971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4274891 [patent_doc_number] => 06281043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Fabrication of hybrid semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/382131 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7440 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281043.pdf [firstpage_image] =>[orig_patent_app_number] => 382131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4328648 [patent_doc_number] => 06312972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Pre-bond encapsulation of area array terminated chip and wafer scale packages' [patent_app_type] => 1 [patent_app_number] => 9/370732 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2226 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312972.pdf [firstpage_image] =>[orig_patent_app_number] => 370732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4347304 [patent_doc_number] => 06214640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method of manufacturing a plurality of semiconductor packages' [patent_app_type] => 1 [patent_app_number] => 9/366152 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 97 [patent_no_of_words] => 12061 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214640.pdf [firstpage_image] =>[orig_patent_app_number] => 366152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258214 [patent_doc_number] => 06258623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Low profile multi-IC chip package connector' [patent_app_type] => 1 [patent_app_number] => 9/349522 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5334 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258623.pdf [firstpage_image] =>[orig_patent_app_number] => 349522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459230 [patent_doc_number] => 06391678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for controlling solderability of a conductor and conductor formed thereby' [patent_app_type] => B1 [patent_app_number] => 09/344971 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391678.pdf [firstpage_image] =>[orig_patent_app_number] => 09344971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4353124 [patent_doc_number] => 06218203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method of producing a contact structure' [patent_app_type] => 1 [patent_app_number] => 9/344851 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 53 [patent_no_of_words] => 7023 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218203.pdf [firstpage_image] =>[orig_patent_app_number] => 344851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4234609 [patent_doc_number] => 06165806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Fault isolation within an inner lead bond region of a .mu.BGA (micro ball grid array) package for an integrated circuit die' [patent_app_type] => 1 [patent_app_number] => 9/340221 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3312 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165806.pdf [firstpage_image] =>[orig_patent_app_number] => 340221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1440958 [patent_doc_number] => 06335223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for producing a resin-sealed semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/339422 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 8697 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335223.pdf [firstpage_image] =>[orig_patent_app_number] => 09339422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523669 [patent_doc_number] => 06352897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of improving edge recess problem of shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/329111 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1832 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352897.pdf [firstpage_image] =>[orig_patent_app_number] => 09329111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380817 [patent_doc_number] => 06294402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method for attaching an integrated circuit chip to a substrate and an integrated circuit chip useful therein' [patent_app_type] => 1 [patent_app_number] => 9/327772 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2189 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294402.pdf [firstpage_image] =>[orig_patent_app_number] => 327772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4353268 [patent_doc_number] => 06218213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Microelectronic components with frangible lead sections' [patent_app_type] => 1 [patent_app_number] => 9/325262 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5525 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218213.pdf [firstpage_image] =>[orig_patent_app_number] => 325262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407920 [patent_doc_number] => 06309910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Microelectronic components with frangible lead sections' [patent_app_type] => 1 [patent_app_number] => 9/313402 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6212 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309910.pdf [firstpage_image] =>[orig_patent_app_number] => 313402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269996 [patent_doc_number] => 06245637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'STI process' [patent_app_type] => 1 [patent_app_number] => 9/307841 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245637.pdf [firstpage_image] =>[orig_patent_app_number] => 307841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4406716 [patent_doc_number] => 06238938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Methods of making microelectronic connections with liquid conductive elements' [patent_app_type] => 1 [patent_app_number] => 9/305028 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 12714 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238938.pdf [firstpage_image] =>[orig_patent_app_number] => 305028 [rel_patent_id] =>[rel_patent_doc_number] =>)