Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4271345
[patent_doc_number] => 06323105
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure'
[patent_app_type] => 1
[patent_app_number] => 9/188822
[patent_app_country] => US
[patent_app_date] => 1998-11-09
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[pdf_file] => patents/06/323/06323105.pdf
[firstpage_image] =>[orig_patent_app_number] => 188822
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/188822 | Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure | Nov 8, 1998 | Issued |
Array
(
[id] => 4303354
[patent_doc_number] => 06187692
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Method for forming an insulating film'
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[patent_app_date] => 1998-11-05
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[firstpage_image] =>[orig_patent_app_number] => 187112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187112 | Method for forming an insulating film | Nov 4, 1998 | Issued |
Array
(
[id] => 4234066
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[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Process for recess-free planarization of shallow trench isolation'
[patent_app_type] => 1
[patent_app_number] => 9/187302
[patent_app_country] => US
[patent_app_date] => 1998-11-05
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Array
(
[id] => 4087691
[patent_doc_number] => 06133148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Method of depositing film for semiconductor device in single wafer type apparatus using a lamp heating method'
[patent_app_type] => 1
[patent_app_number] => 9/185093
[patent_app_country] => US
[patent_app_date] => 1998-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 185093
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/185093 | Method of depositing film for semiconductor device in single wafer type apparatus using a lamp heating method | Nov 2, 1998 | Issued |
Array
(
[id] => 4294473
[patent_doc_number] => 06197701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Lightly nitridation surface for preparing thin-gate oxides'
[patent_app_type] => 1
[patent_app_number] => 9/177191
[patent_app_country] => US
[patent_app_date] => 1998-10-23
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[firstpage_image] =>[orig_patent_app_number] => 177191
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/177191 | Lightly nitridation surface for preparing thin-gate oxides | Oct 22, 1998 | Issued |
Array
(
[id] => 4318360
[patent_doc_number] => 06248611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'LOC semiconductor assembled with room temperature adhesive'
[patent_app_type] => 1
[patent_app_number] => 9/176967
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[patent_app_date] => 1998-10-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176967 | LOC semiconductor assembled with room temperature adhesive | Oct 21, 1998 | Issued |
Array
(
[id] => 4259506
[patent_doc_number] => 06204203
[patent_country] => US
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[patent_issue_date] => 2001-03-20
[patent_title] => 'Post deposition treatment of dielectric films for interface control'
[patent_app_type] => 1
[patent_app_number] => 9/172582
[patent_app_country] => US
[patent_app_date] => 1998-10-14
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[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/204/06204203.pdf
[firstpage_image] =>[orig_patent_app_number] => 172582
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172582 | Post deposition treatment of dielectric films for interface control | Oct 13, 1998 | Issued |
Array
(
[id] => 4359209
[patent_doc_number] => 06169022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Method of forming projection electrodes'
[patent_app_type] => 1
[patent_app_number] => 9/168881
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/169/06169022.pdf
[firstpage_image] =>[orig_patent_app_number] => 168881
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168881 | Method of forming projection electrodes | Oct 8, 1998 | Issued |
Array
(
[id] => 4101206
[patent_doc_number] => 06100112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Method of manufacturing a tape carrier with bump'
[patent_app_type] => 1
[patent_app_number] => 9/167012
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[firstpage_image] =>[orig_patent_app_number] => 167012
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167012 | Method of manufacturing a tape carrier with bump | Oct 5, 1998 | Issued |
Array
(
[id] => 4188348
[patent_doc_number] => 06153480
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Advanced trench sidewall oxide for shallow trench technology'
[patent_app_type] => 1
[patent_app_number] => 9/164112
[patent_app_country] => US
[patent_app_date] => 1998-09-30
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[firstpage_image] =>[orig_patent_app_number] => 164112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164112 | Advanced trench sidewall oxide for shallow trench technology | Sep 29, 1998 | Issued |
Array
(
[id] => 4312953
[patent_doc_number] => 06242345
[patent_country] => US
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[patent_issue_date] => 2001-06-05
[patent_title] => 'Batch process for forming metal plugs in a dielectric layer of a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 9/164393
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[firstpage_image] =>[orig_patent_app_number] => 164393
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164393 | Batch process for forming metal plugs in a dielectric layer of a semiconductor wafer | Sep 29, 1998 | Issued |
Array
(
[id] => 4172137
[patent_doc_number] => 06083772
[patent_country] => US
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[patent_title] => 'Method of mounting a power semiconductor die on a substrate'
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Array
(
[id] => 4294249
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[patent_title] => 'Method for manufacturing a semiconductor device'
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Array
(
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Array
(
[id] => 4246619
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[patent_issue_date] => 2000-10-24
[patent_title] => 'Methods for forming phosphorus- and/or boron-containing silica layers on substrates'
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Array
(
[id] => 4271291
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[patent_title] => 'Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers'
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Array
(
[id] => 4117455
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[patent_title] => 'Method of reducing spiral defects by adding an isopropyl alcohol rinse step before depositing sog'
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Array
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Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 097882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/097882 | Electrostatic protected substrate | Jun 14, 1998 | Issued |