Search

Marina Annette Tietjen

Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3799
Total Applications
1026
Issued Applications
731
Pending Applications
46
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4087849 [patent_doc_number] => 06133160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for reforming undercoating surface and method for production of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/095751 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 8652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133160.pdf [firstpage_image] =>[orig_patent_app_number] => 095751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095751
Method for reforming undercoating surface and method for production of semiconductor device Jun 10, 1998 Issued
Array ( [id] => 3943215 [patent_doc_number] => 05976910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Electronic device assembly and a manufacturing method of the same' [patent_app_type] => 1 [patent_app_number] => 9/089131 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 4199 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976910.pdf [firstpage_image] =>[orig_patent_app_number] => 089131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089131
Electronic device assembly and a manufacturing method of the same Jun 1, 1998 Issued
Array ( [id] => 4234010 [patent_doc_number] => 06074927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Shallow trench isolation formation with trench wall spacer' [patent_app_type] => 1 [patent_app_number] => 9/087662 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3222 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074927.pdf [firstpage_image] =>[orig_patent_app_number] => 087662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087662
Shallow trench isolation formation with trench wall spacer May 31, 1998 Issued
Array ( [id] => 4318708 [patent_doc_number] => 06248636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for forming contact holes of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/086762 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 1556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248636.pdf [firstpage_image] =>[orig_patent_app_number] => 086762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086762
Method for forming contact holes of semiconductor memory device May 27, 1998 Issued
Array ( [id] => 4097876 [patent_doc_number] => 06048771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Shallow trench isolation technique' [patent_app_type] => 1 [patent_app_number] => 9/085207 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1556 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048771.pdf [firstpage_image] =>[orig_patent_app_number] => 085207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085207
Shallow trench isolation technique May 26, 1998 Issued
Array ( [id] => 4246424 [patent_doc_number] => 06136691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'In situ plasma clean for tungsten etching back' [patent_app_type] => 1 [patent_app_number] => 9/085322 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1298 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136691.pdf [firstpage_image] =>[orig_patent_app_number] => 085322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085322
In situ plasma clean for tungsten etching back May 25, 1998 Issued
Array ( [id] => 4356809 [patent_doc_number] => 06190945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Integrated heat sink' [patent_app_type] => 1 [patent_app_number] => 9/082953 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2797 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190945.pdf [firstpage_image] =>[orig_patent_app_number] => 082953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082953
Integrated heat sink May 20, 1998 Issued
Array ( [id] => 4238097 [patent_doc_number] => 06080628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method of forming shallow trench isolation for integrated circuit applications' [patent_app_type] => 1 [patent_app_number] => 9/079602 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1763 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080628.pdf [firstpage_image] =>[orig_patent_app_number] => 079602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079602
Method of forming shallow trench isolation for integrated circuit applications May 14, 1998 Issued
Array ( [id] => 4359095 [patent_doc_number] => 06255229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for forming semiconductor dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/074780 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1695 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255229.pdf [firstpage_image] =>[orig_patent_app_number] => 074780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074780
Method for forming semiconductor dielectric layer May 7, 1998 Issued
Array ( [id] => 4002707 [patent_doc_number] => 06004843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 9/073951 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2835 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004843.pdf [firstpage_image] =>[orig_patent_app_number] => 073951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073951
Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip May 6, 1998 Issued
Array ( [id] => 4188335 [patent_doc_number] => 06153479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of fabricating shallow trench isolation structures' [patent_app_type] => 1 [patent_app_number] => 9/074959 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1139 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153479.pdf [firstpage_image] =>[orig_patent_app_number] => 074959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074959
Method of fabricating shallow trench isolation structures May 6, 1998 Issued
Array ( [id] => 4131232 [patent_doc_number] => 06121097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/072903 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 30 [patent_no_of_words] => 5505 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121097.pdf [firstpage_image] =>[orig_patent_app_number] => 072903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072903
Semiconductor device manufacturing method May 4, 1998 Issued
Array ( [id] => 4188362 [patent_doc_number] => 06153481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for forming an isolation insulating film for internal elements of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/071163 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3349 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153481.pdf [firstpage_image] =>[orig_patent_app_number] => 071163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071163
Method for forming an isolation insulating film for internal elements of a semiconductor device May 3, 1998 Issued
Array ( [id] => 4235322 [patent_doc_number] => 06165854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method to form shallow trench isolation with an oxynitride buffer layer' [patent_app_type] => 1 [patent_app_number] => 9/072290 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165854.pdf [firstpage_image] =>[orig_patent_app_number] => 072290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072290
Method to form shallow trench isolation with an oxynitride buffer layer May 3, 1998 Issued
Array ( [id] => 4153096 [patent_doc_number] => 06107144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for forming field oxide of semiconductor device and the semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/070911 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1635 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107144.pdf [firstpage_image] =>[orig_patent_app_number] => 070911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070911
Method for forming field oxide of semiconductor device and the semiconductor device May 3, 1998 Issued
Array ( [id] => 4343390 [patent_doc_number] => 06284563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of making compliant microelectronic assemblies' [patent_app_type] => 1 [patent_app_number] => 9/071412 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 9733 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284563.pdf [firstpage_image] =>[orig_patent_app_number] => 071412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071412
Method of making compliant microelectronic assemblies Apr 30, 1998 Issued
Array ( [id] => 4130144 [patent_doc_number] => 06033961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Isolation trench fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/071051 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2501 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033961.pdf [firstpage_image] =>[orig_patent_app_number] => 071051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071051
Isolation trench fabrication process Apr 29, 1998 Issued
Array ( [id] => 4232994 [patent_doc_number] => 06117740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of forming a shallow trench isolation by using PE-oxide and PE-nitride multi-layer' [patent_app_type] => 1 [patent_app_number] => 9/056553 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1762 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117740.pdf [firstpage_image] =>[orig_patent_app_number] => 056553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056553
Method of forming a shallow trench isolation by using PE-oxide and PE-nitride multi-layer Apr 6, 1998 Issued
Array ( [id] => 4152550 [patent_doc_number] => 06107107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Analyzing an electronic circuit formed upon a frontside surface of a semiconductor substrate by detecting radiation exiting a backside surface coated with an antireflective material' [patent_app_type] => 1 [patent_app_number] => 9/052221 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9203 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107107.pdf [firstpage_image] =>[orig_patent_app_number] => 052221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052221
Analyzing an electronic circuit formed upon a frontside surface of a semiconductor substrate by detecting radiation exiting a backside surface coated with an antireflective material Mar 30, 1998 Issued
Array ( [id] => 3910784 [patent_doc_number] => 06001696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Trench isolation methods including plasma chemical vapor deposition and lift off' [patent_app_type] => 1 [patent_app_number] => 9/052453 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2591 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001696.pdf [firstpage_image] =>[orig_patent_app_number] => 052453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052453
Trench isolation methods including plasma chemical vapor deposition and lift off Mar 30, 1998 Issued
Menu