Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4087849
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[patent_issue_date] => 2000-10-17
[patent_title] => 'Method for reforming undercoating surface and method for production of semiconductor device'
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[patent_app_number] => 9/095751
[patent_app_country] => US
[patent_app_date] => 1998-06-11
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Array
(
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Electronic device assembly and a manufacturing method of the same'
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[patent_app_date] => 1998-06-02
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Array
(
[id] => 4234010
[patent_doc_number] => 06074927
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[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Shallow trench isolation formation with trench wall spacer'
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[patent_app_number] => 9/087662
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[patent_app_date] => 1998-06-01
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Method for forming contact holes of semiconductor memory device'
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[patent_app_number] => 9/086762
[patent_app_country] => US
[patent_app_date] => 1998-05-28
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Array
(
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Array
(
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[patent_issue_date] => 2000-10-24
[patent_title] => 'In situ plasma clean for tungsten etching back'
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Array
(
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[patent_title] => 'Integrated heat sink'
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[firstpage_image] =>[orig_patent_app_number] => 082953
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/082953 | Integrated heat sink | May 20, 1998 | Issued |
Array
(
[id] => 4238097
[patent_doc_number] => 06080628
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[patent_issue_date] => 2000-06-27
[patent_title] => 'Method of forming shallow trench isolation for integrated circuit applications'
[patent_app_type] => 1
[patent_app_number] => 9/079602
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[patent_app_date] => 1998-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/079602 | Method of forming shallow trench isolation for integrated circuit applications | May 14, 1998 | Issued |
Array
(
[id] => 4359095
[patent_doc_number] => 06255229
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[patent_issue_date] => 2001-07-03
[patent_title] => 'Method for forming semiconductor dielectric layer'
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Array
(
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[patent_title] => 'Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip'
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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