Marina Annette Tietjen
Examiner (ID: 17491, Phone: (571)270-5422 , Office: P/3753 )
Most Active Art Unit | 3753 |
Art Unit(s) | 3753, 3799 |
Total Applications | 1026 |
Issued Applications | 731 |
Pending Applications | 46 |
Abandoned Applications | 249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4116911
[patent_doc_number] => 06071793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect'
[patent_app_type] => 1
[patent_app_number] => 9/017141
[patent_app_country] => US
[patent_app_date] => 1998-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/071/06071793.pdf
[firstpage_image] =>[orig_patent_app_number] => 017141
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017141 | Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect | Feb 1, 1998 | Issued |
Array
(
[id] => 4215004
[patent_doc_number] => 06110821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Method for forming titanium silicide in situ'
[patent_app_type] => 1
[patent_app_number] => 9/013823
[patent_app_country] => US
[patent_app_date] => 1998-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110821.pdf
[firstpage_image] =>[orig_patent_app_number] => 013823
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/013823 | Method for forming titanium silicide in situ | Jan 26, 1998 | Issued |
Array
(
[id] => 4029209
[patent_doc_number] => 05994169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Lead frame for integrated circuits and process of packaging'
[patent_app_type] => 1
[patent_app_number] => 9/012753
[patent_app_country] => US
[patent_app_date] => 1998-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/994/05994169.pdf
[firstpage_image] =>[orig_patent_app_number] => 012753
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/012753 | Lead frame for integrated circuits and process of packaging | Jan 22, 1998 | Issued |
Array
(
[id] => 3936918
[patent_doc_number] => 05981310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Multi-chip heat-sink cap assembly'
[patent_app_type] => 1
[patent_app_number] => 9/012071
[patent_app_country] => US
[patent_app_date] => 1998-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4143
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[pdf_file] => patents/05/981/05981310.pdf
[firstpage_image] =>[orig_patent_app_number] => 012071
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/012071 | Multi-chip heat-sink cap assembly | Jan 21, 1998 | Issued |
Array
(
[id] => 4236644
[patent_doc_number] => 06090641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Electro-thermal nested die-attach design'
[patent_app_type] => 1
[patent_app_number] => 9/009170
[patent_app_country] => US
[patent_app_date] => 1998-01-20
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[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/090/06090641.pdf
[firstpage_image] =>[orig_patent_app_number] => 009170
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/009170 | Electro-thermal nested die-attach design | Jan 19, 1998 | Issued |
Array
(
[id] => 3968522
[patent_doc_number] => 05904498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Connection component with releasable leads'
[patent_app_type] => 1
[patent_app_number] => 9/008283
[patent_app_country] => US
[patent_app_date] => 1998-01-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/904/05904498.pdf
[firstpage_image] =>[orig_patent_app_number] => 008283
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/008283 | Connection component with releasable leads | Jan 15, 1998 | Issued |
Array
(
[id] => 3944393
[patent_doc_number] => 05976990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method for optimization of thin film deposition'
[patent_app_type] => 1
[patent_app_number] => 9/004931
[patent_app_country] => US
[patent_app_date] => 1998-01-09
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/976/05976990.pdf
[firstpage_image] =>[orig_patent_app_number] => 004931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/004931 | Method for optimization of thin film deposition | Jan 8, 1998 | Issued |
Array
(
[id] => 3993822
[patent_doc_number] => 05985725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for manufacturing dual gate oxide layer'
[patent_app_type] => 1
[patent_app_number] => 8/997449
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/985/05985725.pdf
[firstpage_image] =>[orig_patent_app_number] => 997449
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997449 | Method for manufacturing dual gate oxide layer | Dec 22, 1997 | Issued |
Array
(
[id] => 3950560
[patent_doc_number] => 05899728
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method of forming a lithographic mask'
[patent_app_type] => 1
[patent_app_number] => 8/996164
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[firstpage_image] =>[orig_patent_app_number] => 996164
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996164 | Method of forming a lithographic mask | Dec 21, 1997 | Issued |
Array
(
[id] => 4185705
[patent_doc_number] => 06093611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Oxide liner for high reliability with reduced encroachment of the source/drain region'
[patent_app_type] => 1
[patent_app_number] => 8/994502
[patent_app_country] => US
[patent_app_date] => 1997-12-19
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[pdf_file] => patents/06/093/06093611.pdf
[firstpage_image] =>[orig_patent_app_number] => 994502
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994502 | Oxide liner for high reliability with reduced encroachment of the source/drain region | Dec 18, 1997 | Issued |
Array
(
[id] => 4024040
[patent_doc_number] => 05882983
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Trench isolation structure partially bound between a pair of low K dielectric structures'
[patent_app_type] => 1
[patent_app_number] => 8/994143
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Array
(
[id] => 4050644
[patent_doc_number] => 05943585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen'
[patent_app_type] => 1
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Array
(
[id] => 3941775
[patent_doc_number] => 05989975
[patent_country] => US
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Method for manufacturing shallow trench isolation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993501 | Method for manufacturing shallow trench isolation | Dec 17, 1997 | Issued |
Array
(
[id] => 4292074
[patent_doc_number] => 06180466
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[patent_title] => 'Isotropic assisted dual trench etch'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992843 | Isotropic assisted dual trench etch | Dec 17, 1997 | Issued |
Array
(
[id] => 4031389
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[patent_issue_date] => 1999-10-05
[patent_title] => 'Method for forming a CVD film'
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Array
(
[id] => 4007246
[patent_doc_number] => 05888904
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[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Method for manufacturing polysilicon with relatively small line width'
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[pdf_file] => patents/05/888/05888904.pdf
[firstpage_image] =>[orig_patent_app_number] => 991083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991083 | Method for manufacturing polysilicon with relatively small line width | Dec 15, 1997 | Issued |
Array
(
[id] => 4085649
[patent_doc_number] => 06017800
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989941 | Semiconductor device and method of fabricating thereof | Dec 11, 1997 | Issued |
Array
(
[id] => 3941238
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987483 | Semiconductor chip fabrication method and apparatus therefor | Dec 8, 1997 | Issued |