Search

Marissa Liana Ferguson Samreth

Examiner (ID: 166, Phone: (571)272-2163 , Office: P/2854 )

Most Active Art Unit
2854
Art Unit(s)
2854, 2853, 2855
Total Applications
1337
Issued Applications
947
Pending Applications
75
Abandoned Applications
339

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17196029 [patent_doc_number] => 11164794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Semiconductor structures in a wide gate pitch region of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/531114 [patent_app_country] => US [patent_app_date] => 2019-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7952 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531114
Semiconductor structures in a wide gate pitch region of semiconductor devices Aug 3, 2019 Issued
Array ( [id] => 17500894 [patent_doc_number] => 11289604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Method for fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/530954 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3893 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/530954
Method for fabricating a semiconductor device Aug 1, 2019 Issued
Array ( [id] => 15889665 [patent_doc_number] => 10651188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device and a manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/520758 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 52 [patent_no_of_words] => 22227 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520758
Semiconductor device and a manufacturing method thereof Jul 23, 2019 Issued
Array ( [id] => 15093291 [patent_doc_number] => 20190341457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => CONFORMAL DOPING FOR PUNCH THROUGH STOPPER IN FIN FIELD EFFECT TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/515789 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515789
Conformal doping for punch through stopper in fin field effect transistor devices Jul 17, 2019 Issued
Array ( [id] => 15093293 [patent_doc_number] => 20190341458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => CONFORMAL DOPING FOR PUNCH THROUGH STOPPER IN FIN FIELD EFFECT TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/515853 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515853
Conformal doping for punch through stopper in fin field effect transistor devices Jul 17, 2019 Issued
Array ( [id] => 16586129 [patent_doc_number] => 20210020531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL [patent_app_type] => utility [patent_app_number] => 16/511360 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511360
Protruding SN substrate features for epoxy flow control Jul 14, 2019 Issued
Array ( [id] => 15045905 [patent_doc_number] => 20190333957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION LINE [patent_app_type] => utility [patent_app_number] => 16/507623 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507623
Semiconductor package including a redistribution line Jul 9, 2019 Issued
Array ( [id] => 15000093 [patent_doc_number] => 20190319004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => WIRING WITH EXTERNAL TERMINAL [patent_app_type] => utility [patent_app_number] => 16/453842 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453842
Wiring with external terminal Jun 25, 2019 Issued
Array ( [id] => 15274883 [patent_doc_number] => 20190386176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => SUPPORT STRUCTURE FOR LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/441689 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441689
Support structure with sacrifice structure for light-emitting diode and manufacturing method thereof Jun 13, 2019 Issued
Array ( [id] => 15274511 [patent_doc_number] => 20190385990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => DISPLAY MODULE AND ELECTRONIC DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 16/441710 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441710
Display module and electronic device thereof Jun 13, 2019 Issued
Array ( [id] => 15415263 [patent_doc_number] => 20200027954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => SiC-SOI DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/441371 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441371
SiC-SOI device and manufacturing method thereof Jun 13, 2019 Issued
Array ( [id] => 16516022 [patent_doc_number] => 20200395280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => PACKAGE STRUCTURE, RDL STRUCTURE AND METHOD OF FORMIGN THE SAME [patent_app_type] => utility [patent_app_number] => 16/441020 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441020 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441020
Package structure, RDL structure comprising redistribution layer having ground plates and signal lines and method of forming the same Jun 13, 2019 Issued
Array ( [id] => 17395925 [patent_doc_number] => 11244949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Semiconductor device having stacked transistor pairs and method of forming same [patent_app_type] => utility [patent_app_number] => 16/441725 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 14471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441725 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441725
Semiconductor device having stacked transistor pairs and method of forming same Jun 13, 2019 Issued
Array ( [id] => 17032891 [patent_doc_number] => 11094709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/441657 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7785 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441657
Method of manufacturing semiconductor device Jun 13, 2019 Issued
Array ( [id] => 17063310 [patent_doc_number] => 11107923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Source/drain regions of FinFET devices and methods of forming same [patent_app_type] => utility [patent_app_number] => 16/441337 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 8525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441337 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441337
Source/drain regions of FinFET devices and methods of forming same Jun 13, 2019 Issued
Array ( [id] => 16911544 [patent_doc_number] => 11043594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Low parasitic resistance contact structure [patent_app_type] => utility [patent_app_number] => 16/441107 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441107
Low parasitic resistance contact structure Jun 13, 2019 Issued
Array ( [id] => 16699819 [patent_doc_number] => 10950427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Quantum dots and production method thereof [patent_app_type] => utility [patent_app_number] => 16/441574 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14777 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441574 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441574
Quantum dots and production method thereof Jun 13, 2019 Issued
Array ( [id] => 17700288 [patent_doc_number] => 11374022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Distributed FET back-bias network [patent_app_type] => utility [patent_app_number] => 16/441623 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8113 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441623
Distributed FET back-bias network Jun 13, 2019 Issued
Array ( [id] => 15274943 [patent_doc_number] => 20190386206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => CURRENT SENSOR PACKAGE WITH CONTINUOUS INSULATION [patent_app_type] => utility [patent_app_number] => 16/441304 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441304
Current sensor package with continuous insulation Jun 13, 2019 Issued
Array ( [id] => 17032978 [patent_doc_number] => 11094798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Vertical FET with symmetric junctions [patent_app_type] => utility [patent_app_number] => 16/441640 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4189 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441640
Vertical FET with symmetric junctions Jun 13, 2019 Issued
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