
Marissa Liana Ferguson Samreth
Examiner (ID: 166, Phone: (571)272-2163 , Office: P/2854 )
| Most Active Art Unit | 2854 |
| Art Unit(s) | 2854, 2853, 2855 |
| Total Applications | 1337 |
| Issued Applications | 947 |
| Pending Applications | 75 |
| Abandoned Applications | 339 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14178049
[patent_doc_number] => 10263047
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 15/924398
[patent_app_country] => US
[patent_app_date] => 2018-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8394
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924398
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/924398 | Display device | Mar 18, 2018 | Issued |
Array
(
[id] => 13306651
[patent_doc_number] => 20180204862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-19
[patent_title] => EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION
[patent_app_type] => utility
[patent_app_number] => 15/919784
[patent_app_country] => US
[patent_app_date] => 2018-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919784
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/919784 | Extra doped region for back-side deep trench isolation | Mar 12, 2018 | Issued |
Array
(
[id] => 12896314
[patent_doc_number] => 20180190613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-05
[patent_title] => WIRING WITH EXTERNAL TERMINAL
[patent_app_type] => utility
[patent_app_number] => 15/910659
[patent_app_country] => US
[patent_app_date] => 2018-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6465
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910659
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/910659 | Wiring with external terminal | Mar 1, 2018 | Issued |
Array
(
[id] => 15688137
[patent_doc_number] => 20200098732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => TUNABLE WHITE LIGHTING SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 16/483584
[patent_app_country] => US
[patent_app_date] => 2018-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483584
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/483584 | Tunable white lighting systems | Feb 26, 2018 | Issued |
Array
(
[id] => 13306981
[patent_doc_number] => 20180205027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-19
[patent_title] => Method For Producing An Organic CMOS Circuit And Organic CMOS Circuit Protected Against UV Radiation
[patent_app_type] => utility
[patent_app_number] => 15/904344
[patent_app_country] => US
[patent_app_date] => 2018-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4810
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904344
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/904344 | Method for producing an organic CMOS circuit and organic CMOS circuit protected against UV radiation | Feb 23, 2018 | Issued |
Array
(
[id] => 13071317
[patent_doc_number] => 10056447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-21
[patent_title] => Organic light emitting display device
[patent_app_type] => utility
[patent_app_number] => 15/904119
[patent_app_country] => US
[patent_app_date] => 2018-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 10496
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904119
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/904119 | Organic light emitting display device | Feb 22, 2018 | Issued |
Array
(
[id] => 12828598
[patent_doc_number] => 20180168038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-14
[patent_title] => MULTI-STACKED ELECTRONIC DEVICE WITH DEFECT-FREE SOLDER CONNECTION
[patent_app_type] => utility
[patent_app_number] => 15/892740
[patent_app_country] => US
[patent_app_date] => 2018-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2508
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892740
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/892740 | Multi-stacked electronic device with defect-free solder connection | Feb 8, 2018 | Issued |
Array
(
[id] => 15351799
[patent_doc_number] => 20200013791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/483431
[patent_app_country] => US
[patent_app_date] => 2018-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36068
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483431
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/483431 | 3D semiconductor device and structure | Feb 2, 2018 | Issued |
Array
(
[id] => 12800581
[patent_doc_number] => 20180158696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => SEMICONDUCTOR DEVICE WITH RECESS AND METHOD OF MAKING
[patent_app_type] => utility
[patent_app_number] => 15/884926
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28588
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -47
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884926
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884926 | Semiconductor device with recess and method of making | Jan 30, 2018 | Issued |
Array
(
[id] => 14067299
[patent_doc_number] => 10237977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => Multi-stacked electronic device with defect-free solder connection
[patent_app_type] => utility
[patent_app_number] => 15/880155
[patent_app_country] => US
[patent_app_date] => 2018-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2522
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880155
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/880155 | Multi-stacked electronic device with defect-free solder connection | Jan 24, 2018 | Issued |
Array
(
[id] => 13629779
[patent_doc_number] => 20180366442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-20
[patent_title] => HETEROGENOUS 3D CHIP STACK FOR A MOBILE PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/880455
[patent_app_country] => US
[patent_app_date] => 2018-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9366
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880455
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/880455 | Heterogenous 3D chip stack for a mobile processor | Jan 24, 2018 | Issued |
Array
(
[id] => 12778756
[patent_doc_number] => 20180151420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => INTERCONNECT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/878546
[patent_app_country] => US
[patent_app_date] => 2018-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4834
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878546
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/878546 | Interconnect structure | Jan 23, 2018 | Issued |
Array
(
[id] => 12779065
[patent_doc_number] => 20180151523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => METHOD FOR MANUFACTURING INTERCONNECT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/878195
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9289
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878195
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/878195 | Method for manufacturing interconnect structure | Jan 22, 2018 | Issued |
Array
(
[id] => 15108625
[patent_doc_number] => 10475643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-12
[patent_title] => Deposition apparatus and method for manufacturing semiconductor device using the same
[patent_app_type] => utility
[patent_app_number] => 15/876829
[patent_app_country] => US
[patent_app_date] => 2018-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5266
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876829
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/876829 | Deposition apparatus and method for manufacturing semiconductor device using the same | Jan 21, 2018 | Issued |
Array
(
[id] => 13893613
[patent_doc_number] => 10199362
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-02-05
[patent_title] => MicroLED display panel
[patent_app_type] => utility
[patent_app_number] => 15/871696
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2709
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871696
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871696 | MicroLED display panel | Jan 14, 2018 | Issued |
Array
(
[id] => 12736789
[patent_doc_number] => 20180137430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => MODULAR ARRAY OF VERTICALLY INTEGRATED SUPERCONDUCTING QUBIT DEVICES FOR SCALABLE QUANTUM COMPUTING
[patent_app_type] => utility
[patent_app_number] => 15/871443
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9053
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871443
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871443 | Modular array of vertically integrated superconducting qubit devices for scalable quantum computing | Jan 14, 2018 | Issued |
Array
(
[id] => 13470677
[patent_doc_number] => 20180286881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-04
[patent_title] => SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/871818
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871818
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871818 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF | Jan 14, 2018 | Abandoned |
Array
(
[id] => 13909509
[patent_doc_number] => 20190043959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => INTEGRATED CIRCUIT DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/871628
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871628
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871628 | Integrated circuit device | Jan 14, 2018 | Issued |
Array
(
[id] => 14398103
[patent_doc_number] => 10312345
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Transistor having a gate with a variable work function and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/871690
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4440
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871690
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871690 | Transistor having a gate with a variable work function and method for manufacturing the same | Jan 14, 2018 | Issued |
Array
(
[id] => 16495657
[patent_doc_number] => 10861705
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Reduction of line wiggling
[patent_app_type] => utility
[patent_app_number] => 15/871675
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6745
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871675
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871675 | Reduction of line wiggling | Jan 14, 2018 | Issued |