Search

Marivelisse Santiago Cordero

Supervisory Patent Examiner (ID: 3641, Phone: (571)272-7839 , Office: P/2676 )

Most Active Art Unit
2617
Art Unit(s)
2687, 2676, 3700, 2625, 2617
Total Applications
313
Issued Applications
159
Pending Applications
12
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6773357 [patent_doc_number] => 20030016695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'System and method for automatic optimization of optical communication systems' [patent_app_type] => new [patent_app_number] => 10/197109 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6099 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20030016695.pdf [firstpage_image] =>[orig_patent_app_number] => 10197109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197109
System and method for automatic optimization of optical communication systems Jul 16, 2002 Issued
Array ( [id] => 7368013 [patent_doc_number] => 20040015752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Detection of bit errors in maskable content addressable memories' [patent_app_type] => new [patent_app_number] => 10/196763 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015752.pdf [firstpage_image] =>[orig_patent_app_number] => 10196763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196763
Detection of bit errors in maskable content addressable memories Jul 15, 2002 Issued
Array ( [id] => 7368012 [patent_doc_number] => 20040015751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Updating high speed parallel I/O interfaces based on counters' [patent_app_type] => new [patent_app_number] => 10/196384 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015751.pdf [firstpage_image] =>[orig_patent_app_number] => 10196384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196384
Updating high speed parallel I/O interfaces based on counters Jul 15, 2002 Issued
Array ( [id] => 6661159 [patent_doc_number] => 20030135803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Scan cell circuit and scan chain consisting of same for test purpose' [patent_app_type] => new [patent_app_number] => 10/196897 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135803.pdf [firstpage_image] =>[orig_patent_app_number] => 10196897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196897
Scan cell circuit and scan chain consisting of same for test purpose Jul 15, 2002 Issued
Array ( [id] => 7368015 [patent_doc_number] => 20040015753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Detection of bit errors in content addressable memories' [patent_app_type] => new [patent_app_number] => 10/197929 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015753.pdf [firstpage_image] =>[orig_patent_app_number] => 10197929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197929
Detection of bit errors in content addressable memories Jul 15, 2002 Abandoned
Array ( [id] => 680278 [patent_doc_number] => 07089466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Instrumentation system having a reconfigurable instrumentation card with programmable logic and a modular daughter card' [patent_app_type] => utility [patent_app_number] => 10/194720 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6791 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089466.pdf [firstpage_image] =>[orig_patent_app_number] => 10194720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194720
Instrumentation system having a reconfigurable instrumentation card with programmable logic and a modular daughter card Jul 11, 2002 Issued
Array ( [id] => 676250 [patent_doc_number] => 07093190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'System and method for handling parity errors in a data processing system' [patent_app_type] => utility [patent_app_number] => 10/194816 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6534 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093190.pdf [firstpage_image] =>[orig_patent_app_number] => 10194816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194816
System and method for handling parity errors in a data processing system Jul 11, 2002 Issued
Array ( [id] => 6784550 [patent_doc_number] => 20030065998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Test method and test device for electronic memories' [patent_app_type] => new [patent_app_number] => 10/195598 [patent_app_country] => US [patent_app_date] => 2002-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4767 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065998.pdf [firstpage_image] =>[orig_patent_app_number] => 10195598 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195598
Test method and test device for electronic memories Jul 10, 2002 Issued
Array ( [id] => 6693860 [patent_doc_number] => 20030041292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Data recovery circuit for minimizing power consumption by non-integer times oversampling' [patent_app_type] => new [patent_app_number] => 10/193051 [patent_app_country] => US [patent_app_date] => 2002-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8606 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041292.pdf [firstpage_image] =>[orig_patent_app_number] => 10193051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193051
Data recovery circuit for minimizing power consumption by non-integer times oversampling Jul 10, 2002 Issued
Array ( [id] => 6659807 [patent_doc_number] => 20030079169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Automatic repeat request for centralized channel access' [patent_app_type] => new [patent_app_number] => 10/192465 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4608 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20030079169.pdf [firstpage_image] =>[orig_patent_app_number] => 10192465 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192465
Automatic repeat request for centralized channel access Jul 9, 2002 Issued
Array ( [id] => 792821 [patent_doc_number] => 06986086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Method and device for simultaneous testing of a plurality of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/190042 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2947 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986086.pdf [firstpage_image] =>[orig_patent_app_number] => 10190042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190042
Method and device for simultaneous testing of a plurality of integrated circuits Jul 4, 2002 Issued
Array ( [id] => 641287 [patent_doc_number] => 07127653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Apparatus and method for efficient data transport using transparent framing procedure' [patent_app_type] => utility [patent_app_number] => 10/190348 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7267 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/127/07127653.pdf [firstpage_image] =>[orig_patent_app_number] => 10190348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190348
Apparatus and method for efficient data transport using transparent framing procedure Jul 4, 2002 Issued
Array ( [id] => 6431896 [patent_doc_number] => 20020175888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Electrooptical apparatus, method of producing the same and electronic apparatus' [patent_app_type] => new [patent_app_number] => 10/179391 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20913 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175888.pdf [firstpage_image] =>[orig_patent_app_number] => 10179391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179391
Electrooptical apparatus, method of producing the same and electronic apparatus Jun 25, 2002 Issued
Array ( [id] => 421499 [patent_doc_number] => 07278081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-02 [patent_title] => 'Optical transport network frame structure with in-band data channel and forward error correction' [patent_app_type] => utility [patent_app_number] => 10/171297 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7953 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/278/07278081.pdf [firstpage_image] =>[orig_patent_app_number] => 10171297 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171297
Optical transport network frame structure with in-band data channel and forward error correction Jun 12, 2002 Issued
Array ( [id] => 6860128 [patent_doc_number] => 20030091136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method' [patent_app_type] => new [patent_app_number] => 10/164374 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12636 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20030091136.pdf [firstpage_image] =>[orig_patent_app_number] => 10164374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164374
Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method Jun 9, 2002 Issued
Array ( [id] => 695499 [patent_doc_number] => 07076711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Automatic testing of microprocessor bus integrity' [patent_app_type] => utility [patent_app_number] => 10/166207 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2382 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076711.pdf [firstpage_image] =>[orig_patent_app_number] => 10166207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166207
Automatic testing of microprocessor bus integrity Jun 9, 2002 Issued
Array ( [id] => 691051 [patent_doc_number] => 07080302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Semiconductor device and test system therefor' [patent_app_type] => utility [patent_app_number] => 10/163579 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6397 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080302.pdf [firstpage_image] =>[orig_patent_app_number] => 10163579 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163579
Semiconductor device and test system therefor Jun 6, 2002 Issued
Array ( [id] => 6682096 [patent_doc_number] => 20030117960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'DVI link with circuit and method for test' [patent_app_type] => new [patent_app_number] => 10/163058 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5501 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117960.pdf [firstpage_image] =>[orig_patent_app_number] => 10163058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163058
DVI link with circuit and method for test Jun 3, 2002 Issued
Array ( [id] => 958269 [patent_doc_number] => 06957378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/162414 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5782 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957378.pdf [firstpage_image] =>[orig_patent_app_number] => 10162414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162414
Semiconductor memory device Jun 2, 2002 Issued
Array ( [id] => 6665475 [patent_doc_number] => 20030204802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Multiple scan chains with pin sharing' [patent_app_type] => new [patent_app_number] => 10/136670 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5007 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204802.pdf [firstpage_image] =>[orig_patent_app_number] => 10136670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136670
Multiple scan chains with pin sharing Apr 29, 2002 Issued
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