Search

Mark A. Chapman

Examiner (ID: 19279, Phone: (571)272-1381 , Office: P/1721 )

Most Active Art Unit
1753
Art Unit(s)
1754, 1737, 1721, 1507, 1756, 1795, 1753
Total Applications
2639
Issued Applications
2313
Pending Applications
101
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19917814 [patent_doc_number] => 12293184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-06 [patent_title] => Illegal address mask method and device for cores of DSP [patent_app_type] => utility [patent_app_number] => 19/002787 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1077 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002787 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002787
Illegal address mask method and device for cores of DSP Dec 26, 2024 Issued
Array ( [id] => 19878485 [patent_doc_number] => 20250110742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 18/979402 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979402
Processor, method, device and storage medium for data processing Dec 11, 2024 Issued
Array ( [id] => 19892047 [patent_doc_number] => 20250117359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DUAL PIPELINE PARALLEL SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/913758 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913758
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY Oct 10, 2024 Pending
Array ( [id] => 19588704 [patent_doc_number] => 20240386261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NEURAL NETWORK ARCHITECTURE USING CONVOLUTION ENGINES [patent_app_type] => utility [patent_app_number] => 18/788527 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788527
NEURAL NETWORK ARCHITECTURE USING CONVOLUTION ENGINES Jul 29, 2024 Pending
Array ( [id] => 19802661 [patent_doc_number] => 20250068586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK [patent_app_type] => utility [patent_app_number] => 18/784455 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784455
NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK Jul 24, 2024 Pending
Array ( [id] => 19618004 [patent_doc_number] => 20240403684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES [patent_app_type] => utility [patent_app_number] => 18/735514 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735514
Input/output systems and methods for superconducting devices Jun 5, 2024 Issued
Array ( [id] => 19466333 [patent_doc_number] => 20240320003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PROCESSOR AND METHOD FOR ASSIGNING CONFIG ID FOR CORE INCLUDED IN THE SAME [patent_app_type] => utility [patent_app_number] => 18/732492 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732492 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732492
Processor and method for assigning config ID for core included in the same Jun 2, 2024 Issued
Array ( [id] => 19617364 [patent_doc_number] => 20240403044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC [patent_app_type] => utility [patent_app_number] => 18/677140 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677140
Native support for execution of get exponent, get mantisssa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic May 28, 2024 Issued
Array ( [id] => 20388177 [patent_doc_number] => 12487903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Automatic generation of computation kernels for approximating elementary functions [patent_app_type] => utility [patent_app_number] => 18/652846 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5399 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652846
Automatic generation of computation kernels for approximating elementary functions May 1, 2024 Issued
Array ( [id] => 19383063 [patent_doc_number] => 20240272933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SYSTEM AND METHOD TO ACCELERATE REDUCE OPERATIONS IN GRAPHICS PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/626689 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626689
System and method to accelerate reduce operations in graphics processor Apr 3, 2024 Issued
Array ( [id] => 20494263 [patent_doc_number] => 12536133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture [patent_app_type] => utility [patent_app_number] => 18/624877 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624877
Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture Apr 1, 2024 Issued
Array ( [id] => 20203008 [patent_doc_number] => 12405787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Utilizing structured sparsity in systolic arrays [patent_app_type] => utility [patent_app_number] => 18/621539 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621539
Utilizing structured sparsity in systolic arrays Mar 28, 2024 Issued
Array ( [id] => 19320178 [patent_doc_number] => 20240241722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/619570 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619570
APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS Mar 27, 2024 Abandoned
Array ( [id] => 20415794 [patent_doc_number] => 12499080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures [patent_app_type] => utility [patent_app_number] => 18/606924 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606924
Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures Mar 14, 2024 Issued
Array ( [id] => 20440292 [patent_doc_number] => 12511128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Reconfigurable processing-in-memory logic using look-up tables [patent_app_type] => utility [patent_app_number] => 18/606142 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606142
Reconfigurable processing-in-memory logic using look-up tables Mar 14, 2024 Issued
Array ( [id] => 19267728 [patent_doc_number] => 20240211431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TECHNOLOGY FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK [patent_app_type] => utility [patent_app_number] => 18/601598 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601598
Technology for controlling peak power by dividing clock Mar 10, 2024 Issued
Array ( [id] => 20344804 [patent_doc_number] => 12468535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Cooperative instruction prefetch on multicore system [patent_app_type] => utility [patent_app_number] => 18/595866 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595866
Cooperative instruction prefetch on multicore system Mar 4, 2024 Issued
Array ( [id] => 19251133 [patent_doc_number] => 20240202123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STREAMING ENGINE WITH VARIABLE STREAM TEMPLATE FORMAT [patent_app_type] => utility [patent_app_number] => 18/594091 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594091
Streaming engine with variable stream template format Mar 3, 2024 Issued
Array ( [id] => 20137960 [patent_doc_number] => 20250245004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => SIGNIFICAND SHIFTING IN FLOATING POINT PROCESSING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/428137 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428137
Significand shifting in floating point processing operations Jan 30, 2024 Issued
Array ( [id] => 19617366 [patent_doc_number] => 20240403046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Load/Store Unit for a Tensor Engine and Methods for Loading or Storing a Tensor [patent_app_type] => utility [patent_app_number] => 18/423210 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423210
Load/store unit for a tensor engine and methods for loading or storing a tensor Jan 24, 2024 Issued
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