Search

Mark A. Chapman

Examiner (ID: 19279, Phone: (571)272-1381 , Office: P/1721 )

Most Active Art Unit
1753
Art Unit(s)
1754, 1737, 1721, 1507, 1756, 1795, 1753
Total Applications
2639
Issued Applications
2313
Pending Applications
101
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17437682 [patent_doc_number] => 11263015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Microarchitectural sensitive tag flow [patent_app_type] => utility [patent_app_number] => 17/081113 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17189 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081113
Microarchitectural sensitive tag flow Oct 26, 2020 Issued
Array ( [id] => 17550275 [patent_doc_number] => 20220121617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS [patent_app_type] => utility [patent_app_number] => 17/074779 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074779
Method of notifying a process or programmable atomic operation traps Oct 19, 2020 Issued
Array ( [id] => 17454776 [patent_doc_number] => 11269635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => Hardware efficient statistical moment computation [patent_app_type] => utility [patent_app_number] => 17/075140 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075140
Hardware efficient statistical moment computation Oct 19, 2020 Issued
Array ( [id] => 18703753 [patent_doc_number] => 11790267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Apparatus for hardware accelerated machine learning [patent_app_type] => utility [patent_app_number] => 17/070009 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070009
Apparatus for hardware accelerated machine learning Oct 13, 2020 Issued
Array ( [id] => 16600107 [patent_doc_number] => 20210026638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Low Latency Fetch Circuitry for Compute Kernels [patent_app_type] => utility [patent_app_number] => 17/065761 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065761
Low latency fetch circuitry for compute kernels Oct 7, 2020 Issued
Array ( [id] => 16934680 [patent_doc_number] => 20210200569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => METHODS AND SYSTEMS FOR CONVERTING A RELATED GROUP OF PHYSICAL MACHINES TO VIRTUAL MACHINES [patent_app_type] => utility [patent_app_number] => 17/061061 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061061
Methods and systems for converting a related group of physical machines to virtual machines Sep 30, 2020 Issued
Array ( [id] => 16559088 [patent_doc_number] => 20210004237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => GENERATING AND EXECUTING A CONTROL FLOW [patent_app_type] => utility [patent_app_number] => 17/027431 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027431
Generating and executing a control flow Sep 20, 2020 Issued
Array ( [id] => 18925550 [patent_doc_number] => 20240028554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => A CONFIGURABLE PROCESSING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/027078 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18027078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/027078
Configurable processing architecture Sep 17, 2020 Issued
Array ( [id] => 17128532 [patent_doc_number] => 20210303301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Program Execution Assistance Apparatus and Program Execution Assistance Method [patent_app_type] => utility [patent_app_number] => 17/024275 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024275
Program Execution Assistance Apparatus and Program Execution Assistance Method Sep 16, 2020 Abandoned
Array ( [id] => 17572751 [patent_doc_number] => 11321019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Event processing [patent_app_type] => utility [patent_app_number] => 17/017890 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 22713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017890
Event processing Sep 10, 2020 Issued
Array ( [id] => 18046636 [patent_doc_number] => 11520590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching [patent_app_type] => utility [patent_app_number] => 17/010521 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13643 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010521
Detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching Sep 1, 2020 Issued
Array ( [id] => 17288224 [patent_doc_number] => 11204774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Thread-group-scoped gate instruction [patent_app_type] => utility [patent_app_number] => 17/008518 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008518
Thread-group-scoped gate instruction Aug 30, 2020 Issued
Array ( [id] => 17308986 [patent_doc_number] => 11210096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Vector friendly instruction format and execution thereof [patent_app_type] => utility [patent_app_number] => 17/004711 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 78 [patent_no_of_words] => 31692 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004711
Vector friendly instruction format and execution thereof Aug 26, 2020 Issued
Array ( [id] => 16559083 [patent_doc_number] => 20210004232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Energy Efficient Processor Core Architecture for Image Processor [patent_app_type] => utility [patent_app_number] => 17/001097 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001097
Energy efficient processor core architecture for image processor Aug 23, 2020 Issued
Array ( [id] => 17379893 [patent_doc_number] => 11237909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Load exploitation and improved pipelineability of hardware instructions [patent_app_type] => utility [patent_app_number] => 16/999887 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999887
Load exploitation and improved pipelineability of hardware instructions Aug 20, 2020 Issued
Array ( [id] => 17151240 [patent_doc_number] => 11144317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => AC parallelization circuit, AC parallelization method, and parallel information processing device [patent_app_type] => utility [patent_app_number] => 16/997992 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997992
AC parallelization circuit, AC parallelization method, and parallel information processing device Aug 19, 2020 Issued
Array ( [id] => 17469235 [patent_doc_number] => 11275712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => SIMD controller and SIMD predication scheme [patent_app_type] => utility [patent_app_number] => 16/998186 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10024 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998186 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998186
SIMD controller and SIMD predication scheme Aug 19, 2020 Issued
Array ( [id] => 17589493 [patent_doc_number] => 11327766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Instruction dispatch routing [patent_app_type] => utility [patent_app_number] => 16/945404 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11801 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945404
Instruction dispatch routing Jul 30, 2020 Issued
Array ( [id] => 17216386 [patent_doc_number] => 20210349724 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-11-11 [patent_title] => SECURING CONDITIONAL SPECULATIVE INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 16/942591 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942591
Securing conditional speculative instruction execution Jul 28, 2020 Issued
Array ( [id] => 17216386 [patent_doc_number] => 20210349724 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-11-11 [patent_title] => SECURING CONDITIONAL SPECULATIVE INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 16/942591 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942591
Securing conditional speculative instruction execution Jul 28, 2020 Issued
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