Search

Mark A. Chapman

Examiner (ID: 19279, Phone: (571)272-1381 , Office: P/1721 )

Most Active Art Unit
1753
Art Unit(s)
1754, 1737, 1721, 1507, 1756, 1795, 1753
Total Applications
2639
Issued Applications
2313
Pending Applications
101
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17245658 [patent_doc_number] => 20210365402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING MACHINES USING SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 16/900236 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900236
Computing efficient cross channel operations in parallel computing machines using systolic arrays Jun 11, 2020 Issued
Array ( [id] => 17763376 [patent_doc_number] => 20220236988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => MASK OPERATION METHOD FOR EXPLICIT INDEPENDENT MASK REGISTER IN GPU [patent_app_type] => utility [patent_app_number] => 17/618506 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17618506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/618506
Mask operation method for explicit independent mask register in GPU Jun 10, 2020 Issued
Array ( [id] => 17707397 [patent_doc_number] => 20220207404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES [patent_app_type] => utility [patent_app_number] => 17/607278 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17607278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/607278
Input/output systems and methods for superconducting devices Jun 10, 2020 Issued
Array ( [id] => 17165367 [patent_doc_number] => 11151470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Pre-screening and tuning heterojunctions for topological quantum computer [patent_app_type] => utility [patent_app_number] => 16/886670 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886670
Pre-screening and tuning heterojunctions for topological quantum computer May 27, 2020 Issued
Array ( [id] => 17379815 [patent_doc_number] => 11237831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Method and apparatus for permuting streamed data elements [patent_app_type] => utility [patent_app_number] => 16/878611 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 61 [patent_no_of_words] => 38484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878611
Method and apparatus for permuting streamed data elements May 19, 2020 Issued
Array ( [id] => 16470248 [patent_doc_number] => 20200371785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => COMPUTING DEVICE AND NEURAL NETWORK PROCESSOR INCORPORATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/876133 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876133
Computing device and neural network processor incorporating the same May 17, 2020 Issued
Array ( [id] => 17009636 [patent_doc_number] => 20210240797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => ACCELERATOR FOR DENSE AND SPARSE MATRIX COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 16/862370 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862370
Accelerator for dense and sparse matrix computations Apr 28, 2020 Issued
Array ( [id] => 17187249 [patent_doc_number] => 20210334134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Handling Multiple Graphs, Contexts and Programs in a Coarse-Grain Reconfigurable Array Processor [patent_app_type] => utility [patent_app_number] => 16/860070 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860070
Handling multiple graphs, contexts and programs in a coarse-grain reconfigurable array processor Apr 27, 2020 Issued
Array ( [id] => 16780682 [patent_doc_number] => 20210117761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD AND APPARATUS WITH DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 16/857740 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/857740
Method and apparatus with data processing Apr 23, 2020 Issued
Array ( [id] => 17364914 [patent_doc_number] => 11231935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Vectorized sorted-set intersection using conflict-detection SIMD instructions [patent_app_type] => utility [patent_app_number] => 16/846773 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846773
Vectorized sorted-set intersection using conflict-detection SIMD instructions Apr 12, 2020 Issued
Array ( [id] => 17379817 [patent_doc_number] => 11237833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Multiply-accumulate instruction processing method and apparatus [patent_app_type] => utility [patent_app_number] => 16/845606 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10076 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845606
Multiply-accumulate instruction processing method and apparatus Apr 9, 2020 Issued
Array ( [id] => 17091584 [patent_doc_number] => 11119773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Runtime quantum-memory management [patent_app_type] => utility [patent_app_number] => 16/844948 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844948
Runtime quantum-memory management Apr 8, 2020 Issued
Array ( [id] => 17252853 [patent_doc_number] => 11188342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Apparatus and method for speculative conditional move operation [patent_app_type] => utility [patent_app_number] => 16/837824 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15292 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837824
Apparatus and method for speculative conditional move operation Mar 31, 2020 Issued
Array ( [id] => 17128536 [patent_doc_number] => 20210303305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => PROCESSOR HAVING LATENCY SHIFTER AND CONTROLLING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/836864 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836864
Processor having latency shifter and controlling method using the same Mar 30, 2020 Issued
Array ( [id] => 16314582 [patent_doc_number] => 20200293320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => PROCESSOR WITH HARDWARE SUPPORTED MEMORY BUFFER OVERFLOW DETECTION [patent_app_type] => utility [patent_app_number] => 16/835441 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835441
Processor with hardware supported memory buffer overflow detection Mar 30, 2020 Issued
Array ( [id] => 16363132 [patent_doc_number] => 20200319883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS [patent_app_type] => utility [patent_app_number] => 16/831007 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831007
Instruction and logic for tracking fetch performance bottlenecks Mar 25, 2020 Issued
Array ( [id] => 17016935 [patent_doc_number] => 11086574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/831423 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831423 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831423
Machine perception and dense algorithm integrated circuit Mar 25, 2020 Issued
Array ( [id] => 17209583 [patent_doc_number] => 11169956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Networked computer with embedded rings field [patent_app_type] => utility [patent_app_number] => 16/831590 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831590
Networked computer with embedded rings field Mar 25, 2020 Issued
Array ( [id] => 16314578 [patent_doc_number] => 20200293316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 16/815535 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/815535
Computational memory Mar 10, 2020 Issued
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17/434242
Method for validating a data flow system Feb 25, 2020 Issued
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