
Mark A. Chapman
Examiner (ID: 19279, Phone: (571)272-1381 , Office: P/1721 )
| Most Active Art Unit | 1753 |
| Art Unit(s) | 1754, 1737, 1721, 1507, 1756, 1795, 1753 |
| Total Applications | 2639 |
| Issued Applications | 2313 |
| Pending Applications | 101 |
| Abandoned Applications | 234 |
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