Search

Mark A. Laurenzi

Supervisory Patent Examiner (ID: 4424, Phone: (571)270-7878 , Office: P/3754 )

Most Active Art Unit
2894
Art Unit(s)
3754, 2894, 3746, 3748
Total Applications
499
Issued Applications
363
Pending Applications
25
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6304026 [patent_doc_number] => 20100108988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Nanotube-Based Structure and Method of Forming the Structure' [patent_app_type] => utility [patent_app_number] => 12/201530 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7229 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20100108988.pdf [firstpage_image] =>[orig_patent_app_number] => 12201530 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201530
Nanotube-Based Structure and Method of Forming the Structure Aug 28, 2008 Abandoned
Array ( [id] => 6608441 [patent_doc_number] => 20100049342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Method and Apparatus to Facilitate Determining Signal Bounding Frequencies' [patent_app_type] => utility [patent_app_number] => 12/195837 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4392 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20100049342.pdf [firstpage_image] =>[orig_patent_app_number] => 12195837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/195837
Method and apparatus to facilitate determining signal bounding frequencies Aug 20, 2008 Issued
Array ( [id] => 5270433 [patent_doc_number] => 20090074209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Audio Processing for Compressed Digital Television' [patent_app_type] => utility [patent_app_number] => 12/192266 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20090074209.pdf [firstpage_image] =>[orig_patent_app_number] => 12192266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192266
Audio Processing for Compressed Digital Television Aug 14, 2008 Abandoned
Array ( [id] => 6488449 [patent_doc_number] => 20100285619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD FOR MANUFACTURING A SOLID STATE LASER HAVING A PASSIVE\nQ-SWITCH,' [patent_app_type] => utility [patent_app_number] => 12/733550 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2013 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20100285619.pdf [firstpage_image] =>[orig_patent_app_number] => 12733550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/733550
Method for manufacturing a solid state laser having a passive Q-switch Jul 21, 2008 Issued
Array ( [id] => 5290536 [patent_doc_number] => 20090023266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/174780 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20090023266.pdf [firstpage_image] =>[orig_patent_app_number] => 12174780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174780
Method of forming a multi-level interconnect structure by overlay alignment procedures Jul 16, 2008 Issued
Array ( [id] => 5532542 [patent_doc_number] => 20090232330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Apparatus and method for automatic gain control using phase information' [patent_app_type] => utility [patent_app_number] => 12/218063 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6364 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20090232330.pdf [firstpage_image] =>[orig_patent_app_number] => 12218063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/218063
Apparatus and method for automatic gain control using phase information Jul 10, 2008 Issued
Array ( [id] => 91845 [patent_doc_number] => 07732235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Method for fabricating high density pillar structures by double patterning using positive photoresist' [patent_app_type] => utility [patent_app_number] => 12/216108 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 7673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732235.pdf [firstpage_image] =>[orig_patent_app_number] => 12216108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216108
Method for fabricating high density pillar structures by double patterning using positive photoresist Jun 29, 2008 Issued
Array ( [id] => 5461755 [patent_doc_number] => 20090321955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Securing integrated circuit dice to substrates' [patent_app_type] => utility [patent_app_number] => 12/215860 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1733 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321955.pdf [firstpage_image] =>[orig_patent_app_number] => 12215860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215860
Securing integrated circuit dice to substrates Jun 29, 2008 Abandoned
Array ( [id] => 5461589 [patent_doc_number] => 20090321789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Triangle two dimensional complementary patterning of pillars' [patent_app_type] => utility [patent_app_number] => 12/216109 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6158 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321789.pdf [firstpage_image] =>[orig_patent_app_number] => 12216109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216109
Triangle two dimensional complementary patterning of pillars Jun 29, 2008 Issued
Array ( [id] => 5329 [patent_doc_number] => 07812335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Sidewall structured switchable resistor cell' [patent_app_type] => utility [patent_app_number] => 12/216110 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3909 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812335.pdf [firstpage_image] =>[orig_patent_app_number] => 12216110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216110
Sidewall structured switchable resistor cell Jun 29, 2008 Issued
Array ( [id] => 5327921 [patent_doc_number] => 20090108398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Fuse of Semiconductor Device and Method for Forming the Same' [patent_app_type] => utility [patent_app_number] => 12/147730 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108398.pdf [firstpage_image] =>[orig_patent_app_number] => 12147730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147730
Fuse of Semiconductor Device and Method for Forming the Same Jun 26, 2008 Abandoned
Array ( [id] => 43569 [patent_doc_number] => 07781817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Structures, fabrication methods, and design structures for multiple bit flash memory cells' [patent_app_type] => utility [patent_app_number] => 12/146500 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5729 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781817.pdf [firstpage_image] =>[orig_patent_app_number] => 12146500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146500
Structures, fabrication methods, and design structures for multiple bit flash memory cells Jun 25, 2008 Issued
Array ( [id] => 5346102 [patent_doc_number] => 20090001463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'FINFET FIELD EFFECT TRANSISTOR INSULTATED FROM THE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/146166 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001463.pdf [firstpage_image] =>[orig_patent_app_number] => 12146166 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146166
Finfet field effect transistor insulated from the substrate Jun 24, 2008 Issued
Array ( [id] => 5461633 [patent_doc_number] => 20090321833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 12/145616 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2843 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321833.pdf [firstpage_image] =>[orig_patent_app_number] => 12145616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145616
VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC Jun 24, 2008 Abandoned
Array ( [id] => 4488822 [patent_doc_number] => 07884395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/145980 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3682 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884395.pdf [firstpage_image] =>[orig_patent_app_number] => 12145980 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145980
Semiconductor apparatus Jun 24, 2008 Issued
Array ( [id] => 5307490 [patent_doc_number] => 20090014771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/146009 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6814 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014771.pdf [firstpage_image] =>[orig_patent_app_number] => 12146009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146009
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jun 24, 2008 Abandoned
Array ( [id] => 5395130 [patent_doc_number] => 20090315193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'SEMICONDUCTOR CHIP INCLUDING IDENTIFYING MARKS' [patent_app_type] => utility [patent_app_number] => 12/145099 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5036 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315193.pdf [firstpage_image] =>[orig_patent_app_number] => 12145099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145099
Semiconductor chip including identifying marks Jun 23, 2008 Issued
Array ( [id] => 5394998 [patent_doc_number] => 20090315061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'METHODS OF ASSEMBLY FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/145280 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8223 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315061.pdf [firstpage_image] =>[orig_patent_app_number] => 12145280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145280
Methods of assembly for a semiconductor light emitting device package Jun 23, 2008 Issued
Array ( [id] => 5349403 [patent_doc_number] => 20090004764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method for manufacturing SOI substrate and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/213510 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 29913 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20090004764.pdf [firstpage_image] =>[orig_patent_app_number] => 12213510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213510
Method for manufacturing SOI substrate and method for manufacturing semiconductor device Jun 19, 2008 Abandoned
Array ( [id] => 5505782 [patent_doc_number] => 20090078989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device' [patent_app_type] => utility [patent_app_number] => 12/213329 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20090078989.pdf [firstpage_image] =>[orig_patent_app_number] => 12213329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213329
Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device Jun 17, 2008 Abandoned
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