
Mark A. Laurenzi
Supervisory Patent Examiner (ID: 4424, Phone: (571)270-7878 , Office: P/3754 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 3754, 2894, 3746, 3748 |
| Total Applications | 499 |
| Issued Applications | 363 |
| Pending Applications | 25 |
| Abandoned Applications | 119 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6304026
[patent_doc_number] => 20100108988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'Nanotube-Based Structure and Method of Forming the Structure'
[patent_app_type] => utility
[patent_app_number] => 12/201530
[patent_app_country] => US
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[pdf_file] => publications/A1/0108/20100108988.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201530 | Nanotube-Based Structure and Method of Forming the Structure | Aug 28, 2008 | Abandoned |
Array
(
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[patent_doc_number] => 20100049342
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[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'Method and Apparatus to Facilitate Determining Signal Bounding Frequencies'
[patent_app_type] => utility
[patent_app_number] => 12/195837
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195837 | Method and apparatus to facilitate determining signal bounding frequencies | Aug 20, 2008 | Issued |
Array
(
[id] => 5270433
[patent_doc_number] => 20090074209
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[patent_kind] => A1
[patent_issue_date] => 2009-03-19
[patent_title] => 'Audio Processing for Compressed Digital Television'
[patent_app_type] => utility
[patent_app_number] => 12/192266
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/192266 | Audio Processing for Compressed Digital Television | Aug 14, 2008 | Abandoned |
Array
(
[id] => 6488449
[patent_doc_number] => 20100285619
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[patent_kind] => A1
[patent_issue_date] => 2010-11-11
[patent_title] => 'METHOD FOR MANUFACTURING A SOLID STATE LASER HAVING A PASSIVE\nQ-SWITCH,'
[patent_app_type] => utility
[patent_app_number] => 12/733550
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/733550 | Method for manufacturing a solid state laser having a passive Q-switch | Jul 21, 2008 | Issued |
Array
(
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[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/174780 | Method of forming a multi-level interconnect structure by overlay alignment procedures | Jul 16, 2008 | Issued |
Array
(
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[patent_title] => 'Apparatus and method for automatic gain control using phase information'
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Array
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[patent_title] => 'Method for fabricating high density pillar structures by double patterning using positive photoresist'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/216108 | Method for fabricating high density pillar structures by double patterning using positive photoresist | Jun 29, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090321955
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[patent_issue_date] => 2009-12-31
[patent_title] => 'Securing integrated circuit dice to substrates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/215860 | Securing integrated circuit dice to substrates | Jun 29, 2008 | Abandoned |
Array
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[id] => 5461589
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[patent_title] => 'Triangle two dimensional complementary patterning of pillars'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/216109 | Triangle two dimensional complementary patterning of pillars | Jun 29, 2008 | Issued |
Array
(
[id] => 5329
[patent_doc_number] => 07812335
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[patent_issue_date] => 2010-10-12
[patent_title] => 'Sidewall structured switchable resistor cell'
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[patent_app_number] => 12/216110
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/216110 | Sidewall structured switchable resistor cell | Jun 29, 2008 | Issued |
Array
(
[id] => 5327921
[patent_doc_number] => 20090108398
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[patent_title] => 'Fuse of Semiconductor Device and Method for Forming the Same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/147730 | Fuse of Semiconductor Device and Method for Forming the Same | Jun 26, 2008 | Abandoned |
Array
(
[id] => 43569
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[patent_title] => 'Structures, fabrication methods, and design structures for multiple bit flash memory cells'
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Array
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Array
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[patent_title] => 'VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/145616 | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC | Jun 24, 2008 | Abandoned |
Array
(
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Array
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Array
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Array
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[patent_title] => 'Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device'
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