Search

Mark A. Osele

Examiner (ID: 3762, Phone: (571)272-1235 , Office: P/1745 )

Most Active Art Unit
1734
Art Unit(s)
1304, 1745, 1734, 1791, 1301
Total Applications
1756
Issued Applications
1325
Pending Applications
37
Abandoned Applications
394

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20457464 [patent_doc_number] => 12520536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Metal oxide thin film transistor, array substrate and display device [patent_app_type] => utility [patent_app_number] => 18/017649 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1201 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18017649 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/017649
Metal oxide thin film transistor, array substrate and display device Feb 16, 2022 Issued
Array ( [id] => 18767093 [patent_doc_number] => 11817507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor device and method for manufacturing the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/667655 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 93 [patent_no_of_words] => 41135 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667655
Semiconductor device and method for manufacturing the semiconductor device Feb 8, 2022 Issued
Array ( [id] => 20390747 [patent_doc_number] => 12490495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/589079 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589079
Semiconductor device and method for manufacturing the same Jan 30, 2022 Issued
Array ( [id] => 18447130 [patent_doc_number] => 11682706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/588670 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 8725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588670
Semiconductor device Jan 30, 2022 Issued
Array ( [id] => 18528755 [patent_doc_number] => 11715760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/587444 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587444
Semiconductor device Jan 27, 2022 Issued
Array ( [id] => 18600308 [patent_doc_number] => 20230275109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SEMICONDUCTOR IMAGE-SENSING STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/587262 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587262
Semiconductor image-sensing structure and method for forming the same Jan 27, 2022 Issued
Array ( [id] => 17566666 [patent_doc_number] => 20220130815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD OF MANUFACTURING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/571557 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571557
Method of manufacturing package structure Jan 9, 2022 Issued
Array ( [id] => 18146954 [patent_doc_number] => 20230020811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/569040 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569040
Semiconductor module and method for manufacturing the same Jan 4, 2022 Issued
Array ( [id] => 18473178 [patent_doc_number] => 20230207466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => RECESSED AND SELF-ALIGNED BURIED POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/561717 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561717
Recessed and self-aligned buried power rail Dec 23, 2021 Issued
Array ( [id] => 17532848 [patent_doc_number] => 20220111457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TWO-STEP SOLDER-MASK-DEFINED DESIGN [patent_app_type] => utility [patent_app_number] => 17/558546 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558546
Two-step solder-mask-defined design Dec 20, 2021 Issued
Array ( [id] => 17536763 [patent_doc_number] => 20220115372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/555296 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555296
Isolation walls for vertically stacked transistor structures Dec 16, 2021 Issued
Array ( [id] => 19314414 [patent_doc_number] => 12040239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Method for suppressing material warpage by increasing gas density [patent_app_type] => utility [patent_app_number] => 17/546066 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2368 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546066
Method for suppressing material warpage by increasing gas density Dec 8, 2021 Issued
Array ( [id] => 17486211 [patent_doc_number] => 20220093715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/543793 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543793
Display device and method for manufacturing the same Dec 6, 2021 Issued
Array ( [id] => 19038295 [patent_doc_number] => 20240088110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => POWER CONVERTER WITH AT LEAST TWO POWER SEMICONDUCTOR MODULES [patent_app_type] => utility [patent_app_number] => 18/272755 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/272755
POWER CONVERTER WITH AT LEAST TWO POWER SEMICONDUCTOR MODULES Nov 30, 2021 Pending
Array ( [id] => 17692571 [patent_doc_number] => 20220199864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/539521 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539521
Method for manufacturing light-emitting element Nov 30, 2021 Issued
Array ( [id] => 19316024 [patent_doc_number] => 12041861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => RRAM bottom electrode [patent_app_type] => utility [patent_app_number] => 17/533411 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 7520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533411
RRAM bottom electrode Nov 22, 2021 Issued
Array ( [id] => 18520748 [patent_doc_number] => 11710642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/456064 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456064
Semiconductor structure and manufacturing method thereof Nov 21, 2021 Issued
Array ( [id] => 17673204 [patent_doc_number] => 20220186371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DEPOSITION METHOD AND DEPOSITION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/455529 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455529
Deposition method and deposition apparatus Nov 17, 2021 Issued
Array ( [id] => 18304582 [patent_doc_number] => 11626499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/524259 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 6308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524259
Semiconductor device Nov 10, 2021 Issued
Array ( [id] => 19796360 [patent_doc_number] => 12237331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => CMOS logic element including oxide semiconductor [patent_app_type] => utility [patent_app_number] => 17/520853 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4386 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520853
CMOS logic element including oxide semiconductor Nov 7, 2021 Issued
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