Search

Mark A. Williams

Examiner (ID: 10342, Phone: (571)272-7064 , Office: P/3675 )

Most Active Art Unit
3675
Art Unit(s)
3676, 3675, 3674, 3673, 3722, 3209, 3626
Total Applications
2086
Issued Applications
1530
Pending Applications
109
Abandoned Applications
466

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20167040 [patent_doc_number] => 20250259087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => Reconfigurable Quantum Arrays and Quantum Memory for Learning [patent_app_type] => utility [patent_app_number] => 19/048434 [patent_app_country] => US [patent_app_date] => 2025-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19048434 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/048434
Reconfigurable Quantum Arrays and Quantum Memory for Learning Feb 6, 2025 Pending
Array ( [id] => 20139214 [patent_doc_number] => 20250246258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MANAGEMENT OF MEMORY DEVICE DEBUG PROCESSING [patent_app_type] => utility [patent_app_number] => 19/034135 [patent_app_country] => US [patent_app_date] => 2025-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19034135 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/034135
MANAGEMENT OF MEMORY DEVICE DEBUG PROCESSING Jan 21, 2025 Pending
Array ( [id] => 20138054 [patent_doc_number] => 20250245098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => ERROR MANAGEMENT OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 19/023687 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023687 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023687
ERROR MANAGEMENT OF MEMORY DEVICES Jan 15, 2025 Pending
Array ( [id] => 20125004 [patent_doc_number] => 20250240035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => LOW-COMPLEXITY DECODER AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/019250 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19019250 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/019250
LOW-COMPLEXITY DECODER AND OPERATION METHOD THEREOF Jan 12, 2025 Pending
Array ( [id] => 20181187 [patent_doc_number] => 20250265145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => REFINED HARD BIT READ VOLTAGES [patent_app_type] => utility [patent_app_number] => 19/017648 [patent_app_country] => US [patent_app_date] => 2025-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017648 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017648
REFINED HARD BIT READ VOLTAGES Jan 10, 2025 Pending
Array ( [id] => 20095088 [patent_doc_number] => 20250225024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR LATENCY-CRITICAL COHERENCY AND MEMORY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 19/010979 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19010979 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/010979
FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR LATENCY-CRITICAL COHERENCY AND MEMORY INTERCONNECTS Jan 5, 2025 Pending
Array ( [id] => 20601777 [patent_doc_number] => 20260079787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => ERROR CORRECTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/991732 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/991732
ERROR CORRECTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME Dec 22, 2024 Pending
Array ( [id] => 19987680 [patent_doc_number] => 20250125902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => COMMUNICATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/990147 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/990147
COMMUNICATION METHOD AND APPARATUS Dec 19, 2024 Pending
Array ( [id] => 19893849 [patent_doc_number] => 20250119161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DECODING APPARATUS, DECODING METHOD, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/982129 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982129 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/982129
DECODING APPARATUS, DECODING METHOD, AND ELECTRONIC APPARATUS Dec 15, 2024 Pending
Array ( [id] => 20052611 [patent_doc_number] => 20250190833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => METHOD FOR MOVING MAGIC STATES THROUGH BOUNDARY EXTENSION IN ROTATED SURFACE CODE [patent_app_type] => utility [patent_app_number] => 18/970872 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970872
METHOD FOR MOVING MAGIC STATES THROUGH BOUNDARY EXTENSION IN ROTATED SURFACE CODE Dec 4, 2024 Pending
Array ( [id] => 20222768 [patent_doc_number] => 20250285699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => TEST DEVICE AND TEST METHOD FOR MEASURING TIMING SPECIFICATIONS OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/970531 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970531
TEST DEVICE AND TEST METHOD FOR MEASURING TIMING SPECIFICATIONS OF MEMORY DEVICE Dec 4, 2024 Pending
Array ( [id] => 19822064 [patent_doc_number] => 20250080271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => PRIORITY BASED MAPPING OF ENCODED BITS TO SYMBOLS [patent_app_type] => utility [patent_app_number] => 18/953968 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/953968
PRIORITY BASED MAPPING OF ENCODED BITS TO SYMBOLS Nov 19, 2024 Pending
Array ( [id] => 20501710 [patent_doc_number] => 20260031172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => CORRECTIVE READ AGGRESSOR INFORMATION FOR ERROR CORRECTION CODE ENHANCEMENT [patent_app_type] => utility [patent_app_number] => 18/939061 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939061
CORRECTIVE READ AGGRESSOR INFORMATION FOR ERROR CORRECTION CODE ENHANCEMENT Nov 5, 2024 Pending
Array ( [id] => 20512522 [patent_doc_number] => 20260036623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => FLIP-FLOPS FOR CIRCUIT TESTING BASED ON SCAN CHAINS [patent_app_type] => utility [patent_app_number] => 18/938024 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938024 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938024
FLIP-FLOPS FOR CIRCUIT TESTING BASED ON SCAN CHAINS Nov 4, 2024 Pending
Array ( [id] => 19756593 [patent_doc_number] => 20250045158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Data Writing Method and Processing System [patent_app_type] => utility [patent_app_number] => 18/920383 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920383
Data Writing Method and Processing System Oct 17, 2024 Pending
Array ( [id] => 20654606 [patent_doc_number] => 20260106631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => Fast BF Decoder with Column Zone Convergence Detection [patent_app_type] => utility [patent_app_number] => 18/912466 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18912466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/912466
Fast BF Decoder with Column Zone Convergence Detection Oct 9, 2024 Pending
Array ( [id] => 20630372 [patent_doc_number] => 20260094660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => Data Storage Device and Method for Dynamic Bit-Error-Rate Estimation Scan (BES) [patent_app_type] => utility [patent_app_number] => 18/903283 [patent_app_country] => US [patent_app_date] => 2024-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18903283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/903283
Data storage device and method for dynamic bit-error-rate estimation scan (BES) Sep 30, 2024 Issued
Array ( [id] => 19694970 [patent_doc_number] => 20250013515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/891216 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891216
Method for encoded diagnostics in a functional safety system Sep 19, 2024 Issued
Array ( [id] => 19688992 [patent_doc_number] => 20250007537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/887114 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887114
EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES Sep 16, 2024 Pending
Array ( [id] => 19820737 [patent_doc_number] => 20250078944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => IMAGE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/815077 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815077
IMAGE DISPLAY DEVICE Aug 25, 2024 Pending
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