Mark Alan Sager

Array ( [id] => 700237 [patent_doc_number] => 07067909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Multi-layer integrated semiconductor structure having an electrical shielding portion' [patent_app_type] => utility [patent_app_number] => 10/749096 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6745 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067909.pdf [firstpage_image] =>[orig_patent_app_number] => 10749096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7241756 [patent_doc_number] => 20050072996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Ferroelectric thin film, method of manufacturing the same, ferroelectric memory device and ferroelectric piezoelectric device' [patent_app_type] => utility [patent_app_number] => 10/743716 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4649 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20050072996.pdf [firstpage_image] =>[orig_patent_app_number] => 10743716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 702982 [patent_doc_number] => 07064358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Triggered back-to-back diodes for ESD protection in triple-well CMOS process' [patent_app_type] => utility [patent_app_number] => 10/743596 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4119 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064358.pdf [firstpage_image] =>[orig_patent_app_number] => 10743596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 687835 [patent_doc_number] => 07078795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'High voltage module and method for producing same' [patent_app_type] => utility [patent_app_number] => 10/742366 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3289 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078795.pdf [firstpage_image] =>[orig_patent_app_number] => 10742366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 979379 [patent_doc_number] => 06930385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Cascaded die mountings with spring-loaded contact-bond options' [patent_app_type] => utility [patent_app_number] => 10/738746 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3116 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930385.pdf [firstpage_image] =>[orig_patent_app_number] => 10738746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 507940 [patent_doc_number] => 07202542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Semiconductor structure with metal migration semiconductor barrier layers and method of forming the same' [patent_app_type] => utility [patent_app_number] => 10/739755 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5394 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202542.pdf [firstpage_image] =>[orig_patent_app_number] => 10739755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375667 [patent_doc_number] => 20040178501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Tape circuit substrate having wavy beam leads and semiconductor chip package using the same' [patent_app_type] => new [patent_app_number] => 10/739456 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4593 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178501.pdf [firstpage_image] =>[orig_patent_app_number] => 10739456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 664163 [patent_doc_number] => 07102235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Conformal lining layers for damascene metallization' [patent_app_type] => utility [patent_app_number] => 10/737315 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10470 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102235.pdf [firstpage_image] =>[orig_patent_app_number] => 10737315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 673037 [patent_doc_number] => 07091589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Multilayer wiring board and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 10/497536 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 63 [patent_no_of_words] => 26186 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091589.pdf [firstpage_image] =>[orig_patent_app_number] => 10497536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 535127 [patent_doc_number] => 07180088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Nitride based semiconductor light-emitting device' [patent_app_type] => utility [patent_app_number] => 10/731336 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4872 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180088.pdf [firstpage_image] =>[orig_patent_app_number] => 10731336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 783400 [patent_doc_number] => 06992345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Integrated semiconductor memory with a selection transistor formed at a ridge' [patent_app_type] => utility [patent_app_number] => 10/727595 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992345.pdf [firstpage_image] =>[orig_patent_app_number] => 10727595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154509 [patent_doc_number] => 20050082652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Integrated circuit housing' [patent_app_type] => utility [patent_app_number] => 10/716196 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082652.pdf [firstpage_image] =>[orig_patent_app_number] => 10716196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6903501 [patent_doc_number] => 20050098896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Integration film scheme for copper / low-k interconnect' [patent_app_type] => utility [patent_app_number] => 10/706156 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5493 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098896.pdf [firstpage_image] =>[orig_patent_app_number] => 10706156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6915615 [patent_doc_number] => 20050093176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Bonding pad structure' [patent_app_type] => utility [patent_app_number] => 10/696186 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5608 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093176.pdf [firstpage_image] =>[orig_patent_app_number] => 10696186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 683033 [patent_doc_number] => 07081668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Flip chip molded/exposed die process and package structure' [patent_app_type] => utility [patent_app_number] => 10/693217 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3201 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081668.pdf [firstpage_image] =>[orig_patent_app_number] => 10693217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1044064 [patent_doc_number] => 06867444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Semiconductor substrate incorporating a neutron conversion layer' [patent_app_type] => utility [patent_app_number] => 10/693846 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867444.pdf [firstpage_image] =>[orig_patent_app_number] => 10693846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944341 [patent_doc_number] => 06967395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Mounting for a package containing a chip' [patent_app_type] => utility [patent_app_number] => 10/688138 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4703 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967395.pdf [firstpage_image] =>[orig_patent_app_number] => 10688138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 524967 [patent_doc_number] => 07179205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Differential motion machine' [patent_app_type] => utility [patent_app_number] => 10/685625 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 17789 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/179/07179205.pdf [firstpage_image] =>[orig_patent_app_number] => 10685625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7159484 [patent_doc_number] => 20040075143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same' [patent_app_type] => new [patent_app_number] => 10/685116 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7476 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075143.pdf [firstpage_image] =>[orig_patent_app_number] => 10685116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1005927 [patent_doc_number] => 06906357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection' [patent_app_type] => utility [patent_app_number] => 10/683625 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2835 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906357.pdf [firstpage_image] =>[orig_patent_app_number] => 10683625 [rel_patent_id] =>[rel_patent_doc_number] =>)