Mark Alan Sager

Array ( [id] => 6269847 [patent_doc_number] => 20020105098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Semiconductor device and manufacturing method of the same' [patent_app_type] => new [patent_app_number] => 09/909975 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5984 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105098.pdf [firstpage_image] =>[orig_patent_app_number] => 09909975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6733379 [patent_doc_number] => 20030011014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Capacitor with high dielectric constant materials and method of making' [patent_app_type] => new [patent_app_number] => 09/903160 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2781 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20030011014.pdf [firstpage_image] =>[orig_patent_app_number] => 09903160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6476753 [patent_doc_number] => 20020024130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Electronic component and electronic equipment using the same' [patent_app_type] => new [patent_app_number] => 09/897423 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3083 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024130.pdf [firstpage_image] =>[orig_patent_app_number] => 09897423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424162 [patent_doc_number] => 06507065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Doped silicon structure with impression image on opposing roughened surfaces' [patent_app_type] => B2 [patent_app_number] => 09/897258 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6756 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507065.pdf [firstpage_image] =>[orig_patent_app_number] => 09897258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6573223 [patent_doc_number] => 20020014692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Heat conductive silicone composition and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/887266 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5076 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014692.pdf [firstpage_image] =>[orig_patent_app_number] => 09887266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 637811 [patent_doc_number] => 07125763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Silicided buried bitline process for a non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 09/885426 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3453 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/125/07125763.pdf [firstpage_image] =>[orig_patent_app_number] => 09885426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645262 [patent_doc_number] => 06472710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Field MOS transistor and semiconductor integrated circuit including the same' [patent_app_type] => B2 [patent_app_number] => 09/881805 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472710.pdf [firstpage_image] =>[orig_patent_app_number] => 09881805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1228244 [patent_doc_number] => 06696342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Small emitter and base-collector bi-polar transistor' [patent_app_type] => B1 [patent_app_number] => 09/882936 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1687 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696342.pdf [firstpage_image] =>[orig_patent_app_number] => 09882936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1063761 [patent_doc_number] => 06849945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Multi-layered semiconductor device and method for producing the same' [patent_app_type] => utility [patent_app_number] => 09/881005 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849945.pdf [firstpage_image] =>[orig_patent_app_number] => 09881005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 951619 [patent_doc_number] => 06960824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Structure and method for fabrication of a leadless chip carrier' [patent_app_type] => utility [patent_app_number] => 09/878815 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960824.pdf [firstpage_image] =>[orig_patent_app_number] => 09878815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1159530 [patent_doc_number] => 06762463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'MOSFET with SiGe source/drain regions and epitaxial gate dielectric' [patent_app_type] => B2 [patent_app_number] => 09/877906 [patent_app_country] => US [patent_app_date] => 2001-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1498 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762463.pdf [firstpage_image] =>[orig_patent_app_number] => 09877906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630933 [patent_doc_number] => 06635999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method and apparatus for controlling the temperature of a multiparameter light and/or a component thereof using orientation and/or parameter information' [patent_app_type] => B2 [patent_app_number] => 09/877699 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 11813 [patent_no_of_claims] => 121 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635999.pdf [firstpage_image] =>[orig_patent_app_number] => 09877699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1276803 [patent_doc_number] => 06649967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Non-volatile memory device with a floating gate having a tapered protrusion' [patent_app_type] => B2 [patent_app_number] => 09/873226 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 4898 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649967.pdf [firstpage_image] =>[orig_patent_app_number] => 09873226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1420778 [patent_doc_number] => 06512293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Mechanically interlocking ball grid array packages and method of making' [patent_app_type] => B1 [patent_app_number] => 09/875055 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1034 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512293.pdf [firstpage_image] =>[orig_patent_app_number] => 09875055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762027 [patent_doc_number] => 07012311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof' [patent_app_type] => utility [patent_app_number] => 09/866576 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 13184 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012311.pdf [firstpage_image] =>[orig_patent_app_number] => 09866576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7066807 [patent_doc_number] => 20010044926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Wiring connection checking apparatus and method for CAD system and recording medium on which program therefor is recorded' [patent_app_type] => new [patent_app_number] => 09/858484 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2833 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044926.pdf [firstpage_image] =>[orig_patent_app_number] => 09858484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6115725 [patent_doc_number] => 20020174410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method of configuring integrated circuits using greedy algorithm for partitioning of n points in p isothetic rectangles' [patent_app_type] => new [patent_app_number] => 09/858825 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6749 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174410.pdf [firstpage_image] =>[orig_patent_app_number] => 09858825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430742 [patent_doc_number] => 06526546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method for locating faulty elements in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/831832 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 17152 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526546.pdf [firstpage_image] =>[orig_patent_app_number] => 09831832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429847 [patent_doc_number] => 06530067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method for subdividing data of a layout' [patent_app_type] => B2 [patent_app_number] => 09/852682 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1846 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530067.pdf [firstpage_image] =>[orig_patent_app_number] => 09852682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602350 [patent_doc_number] => 06493851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus for indentifying causes of poor silicon-to-simulation correlation' [patent_app_type] => B1 [patent_app_number] => 09/848489 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4448 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493851.pdf [firstpage_image] =>[orig_patent_app_number] => 09848489 [rel_patent_id] =>[rel_patent_doc_number] =>)