Search

Mark Rosenbaum

Examiner (ID: 18547, Phone: (571)272-4523 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3502, 3206, 2899, 3505, 3725, 3209, 3202, 3204, 3201, 3203, 3103
Total Applications
4526
Issued Applications
3830
Pending Applications
109
Abandoned Applications
597

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4154269 [patent_doc_number] => 06103580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method to form ultra-shallow buried-channel MOSFETs' [patent_app_type] => 1 [patent_app_number] => 9/270589 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103580.pdf [firstpage_image] =>[orig_patent_app_number] => 270589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270589
Method to form ultra-shallow buried-channel MOSFETs Mar 17, 1999 Issued
Array ( [id] => 4101654 [patent_doc_number] => 06100143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of making a depleted poly-silicon edged MOSFET structure' [patent_app_type] => 1 [patent_app_number] => 9/267239 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100143.pdf [firstpage_image] =>[orig_patent_app_number] => 267239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267239
Method of making a depleted poly-silicon edged MOSFET structure Mar 11, 1999 Issued
Array ( [id] => 4309995 [patent_doc_number] => 06316299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Formation of laterally diffused metal-oxide semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/262188 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1538 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316299.pdf [firstpage_image] =>[orig_patent_app_number] => 262188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262188
Formation of laterally diffused metal-oxide semiconductor device Mar 3, 1999 Issued
Array ( [id] => 4258697 [patent_doc_number] => 06258655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for improving the resistance degradation of thin film capacitors' [patent_app_type] => 1 [patent_app_number] => 9/259259 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3658 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258655.pdf [firstpage_image] =>[orig_patent_app_number] => 259259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259259
Method for improving the resistance degradation of thin film capacitors Feb 28, 1999 Issued
Array ( [id] => 4258697 [patent_doc_number] => 06258655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for improving the resistance degradation of thin film capacitors' [patent_app_type] => 1 [patent_app_number] => 9/259259 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3658 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258655.pdf [firstpage_image] =>[orig_patent_app_number] => 259259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259259
Method for improving the resistance degradation of thin film capacitors Feb 28, 1999 Issued
Array ( [id] => 4324949 [patent_doc_number] => 06329262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method for producing semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/256738 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3141 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329262.pdf [firstpage_image] =>[orig_patent_app_number] => 256738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256738
Method for producing semiconductor integrated circuit Feb 23, 1999 Issued
Array ( [id] => 4189263 [patent_doc_number] => 06153541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for fabricating an oxynitride layer having anti-reflective properties and low leakage current' [patent_app_type] => 1 [patent_app_number] => 9/256269 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2257 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153541.pdf [firstpage_image] =>[orig_patent_app_number] => 256269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256269
Method for fabricating an oxynitride layer having anti-reflective properties and low leakage current Feb 22, 1999 Issued
Array ( [id] => 1594566 [patent_doc_number] => 06383916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => B1 [patent_app_number] => 09/251183 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5156 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383916.pdf [firstpage_image] =>[orig_patent_app_number] => 09251183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251183
Top layers of metal for high performance IC's Feb 16, 1999 Issued
Array ( [id] => 4419574 [patent_doc_number] => 06177327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method of manufacturing capacitor for mixed-moded circuit device' [patent_app_type] => 1 [patent_app_number] => 9/250628 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177327.pdf [firstpage_image] =>[orig_patent_app_number] => 250628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250628
Method of manufacturing capacitor for mixed-moded circuit device Feb 15, 1999 Issued
Array ( [id] => 4302322 [patent_doc_number] => 06187618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array' [patent_app_type] => 1 [patent_app_number] => 9/249469 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6210 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187618.pdf [firstpage_image] =>[orig_patent_app_number] => 249469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249469
Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array Feb 11, 1999 Issued
Array ( [id] => 7639813 [patent_doc_number] => 06396103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Optimized single side pocket implant location for a field effect transistor' [patent_app_type] => B1 [patent_app_number] => 09/243989 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3828 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396103.pdf [firstpage_image] =>[orig_patent_app_number] => 09243989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243989
Optimized single side pocket implant location for a field effect transistor Feb 2, 1999 Issued
Array ( [id] => 5828714 [patent_doc_number] => 20020068409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'METHOD OF REDUCING JUNCTION CAPACITANCE' [patent_app_type] => new [patent_app_number] => 09/243188 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068409.pdf [firstpage_image] =>[orig_patent_app_number] => 09243188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243188
METHOD OF REDUCING JUNCTION CAPACITANCE Feb 1, 1999 Abandoned
Array ( [id] => 4100435 [patent_doc_number] => 06066572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method of removing carbon contamination on semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/241338 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2327 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066572.pdf [firstpage_image] =>[orig_patent_app_number] => 241338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241338
Method of removing carbon contamination on semiconductor substrate Jan 31, 1999 Issued
Array ( [id] => 4394263 [patent_doc_number] => 06297069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method for supporting during fabrication mechanical members of semi-conductive dies, wafers, and devices and an associated intermediate device assembly' [patent_app_type] => 1 [patent_app_number] => 9/239469 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 8118 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297069.pdf [firstpage_image] =>[orig_patent_app_number] => 239469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239469
Method for supporting during fabrication mechanical members of semi-conductive dies, wafers, and devices and an associated intermediate device assembly Jan 27, 1999 Issued
Array ( [id] => 3945429 [patent_doc_number] => 05953615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Pre-amorphization process for source/drain junction' [patent_app_type] => 1 [patent_app_number] => 9/238359 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953615.pdf [firstpage_image] =>[orig_patent_app_number] => 238359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238359
Pre-amorphization process for source/drain junction Jan 26, 1999 Issued
Array ( [id] => 4381993 [patent_doc_number] => 06294481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/232849 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 44 [patent_no_of_words] => 8716 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294481.pdf [firstpage_image] =>[orig_patent_app_number] => 232849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232849
Semiconductor device and method for manufacturing the same Jan 18, 1999 Issued
Array ( [id] => 4087356 [patent_doc_number] => 06133125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Selective area diffusion control process' [patent_app_type] => 1 [patent_app_number] => 9/226399 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3442 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133125.pdf [firstpage_image] =>[orig_patent_app_number] => 226399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226399
Selective area diffusion control process Jan 5, 1999 Issued
Array ( [id] => 4292849 [patent_doc_number] => 06180521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Process for manufacturing a contact barrier' [patent_app_type] => 1 [patent_app_number] => 9/225598 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3737 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180521.pdf [firstpage_image] =>[orig_patent_app_number] => 225598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225598
Process for manufacturing a contact barrier Jan 5, 1999 Issued
Array ( [id] => 4107220 [patent_doc_number] => 06057181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Thin film transistor and method for fabricating same' [patent_app_type] => 1 [patent_app_number] => 9/225828 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3076 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057181.pdf [firstpage_image] =>[orig_patent_app_number] => 225828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225828
Thin film transistor and method for fabricating same Jan 5, 1999 Issued
Array ( [id] => 4317882 [patent_doc_number] => 06316809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Analog MOSFET devices' [patent_app_type] => 1 [patent_app_number] => 9/226378 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3049 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316809.pdf [firstpage_image] =>[orig_patent_app_number] => 226378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226378
Analog MOSFET devices Jan 5, 1999 Issued
Menu