Mark S. Blouin

Array ( [id] => 8870632 [patent_doc_number] => 08466009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Method of fabricating a semiconductor package with mold lock opening' [patent_app_type] => utility [patent_app_number] => 12/779367 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12779367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6440975 [patent_doc_number] => 20100279468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'LAMINATED FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/763588 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 19288 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20100279468.pdf [firstpage_image] =>[orig_patent_app_number] => 12763588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7511021 [patent_doc_number] => 20110256731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => ' METHOD FOR FABRICATING A GATE DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 12/760297 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256731.pdf [firstpage_image] =>[orig_patent_app_number] => 12760297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8858488 [patent_doc_number] => 08461023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-11 [patent_title] => 'Die singulation method' [patent_app_type] => utility [patent_app_number] => 12/758838 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7354 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6063421 [patent_doc_number] => 20110201192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'METHOD OF PROCESSING BACKSIDE COPPER LAYER FOR SEMICONDUCTOR CHIPS' [patent_app_type] => utility [patent_app_number] => 12/757458 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2810 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20110201192.pdf [firstpage_image] =>[orig_patent_app_number] => 12757458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6512214 [patent_doc_number] => 20100261312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/756178 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261312.pdf [firstpage_image] =>[orig_patent_app_number] => 12756178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7486206 [patent_doc_number] => 20110250751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'METHOD FOR FILLING METAL' [patent_app_type] => utility [patent_app_number] => 12/757017 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2202 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250751.pdf [firstpage_image] =>[orig_patent_app_number] => 12757017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8664331 [patent_doc_number] => 08377792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of forming high capacitance semiconductor capacitors with a single lithography step' [patent_app_type] => utility [patent_app_number] => 12/756097 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 5276 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 632 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8386071 [patent_doc_number] => 08263465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer' [patent_app_type] => utility [patent_app_number] => 12/754408 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7103 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6432741 [patent_doc_number] => 20100187614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'SELECTIVE NITRIDATION OF GATE OXIDES' [patent_app_type] => utility [patent_app_number] => 12/752628 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187614.pdf [firstpage_image] =>[orig_patent_app_number] => 12752628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6264097 [patent_doc_number] => 20100252861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Devices Formed from a Non-Polar Plane of a Crystalline Material and Method of Making the Same' [patent_app_type] => utility [patent_app_number] => 12/753049 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9367 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252861.pdf [firstpage_image] =>[orig_patent_app_number] => 12753049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8064849 [patent_doc_number] => 20110244599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR' [patent_app_type] => utility [patent_app_number] => 12/751927 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8180 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20110244599.pdf [firstpage_image] =>[orig_patent_app_number] => 12751927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7535080 [patent_doc_number] => 08048704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Method of forming a MEMS topped integrated circuit with a stress relief layer' [patent_app_type] => utility [patent_app_number] => 12/750145 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 5356 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/048/08048704.pdf [firstpage_image] =>[orig_patent_app_number] => 12750145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6397114 [patent_doc_number] => 20100304513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD FOR FORMING AN ORGANIC LIGHT EMITTING DIODE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/749637 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20100304513.pdf [firstpage_image] =>[orig_patent_app_number] => 12749637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6432445 [patent_doc_number] => 20100187576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Method of processing resist, semiconductor device, and method of producing the same' [patent_app_type] => utility [patent_app_number] => 12/659970 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8888 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187576.pdf [firstpage_image] =>[orig_patent_app_number] => 12659970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8469732 [patent_doc_number] => 08298910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/732907 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4382 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12732907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7489037 [patent_doc_number] => 20110237051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'PROCESS AND APPARATUS FOR DEPOSITION OF MULTICOMPONENT SEMICONDUCTOR LAYERS' [patent_app_type] => utility [patent_app_number] => 12/748368 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3322 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20110237051.pdf [firstpage_image] =>[orig_patent_app_number] => 12748368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8257586 [patent_doc_number] => 08207067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Method of processing resist, semiconductor device, and method of producing the same' [patent_app_type] => utility [patent_app_number] => 12/659976 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 8892 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7488966 [patent_doc_number] => 20110237013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'Creation of Low-Relief Texture for a Photovoltaic Cell' [patent_app_type] => utility [patent_app_number] => 12/729878 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7310 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20110237013.pdf [firstpage_image] =>[orig_patent_app_number] => 12729878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9286067 [patent_doc_number] => 08642395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Method of making chip-on-lead package' [patent_app_type] => utility [patent_app_number] => 12/727258 [patent_app_country] => US [patent_app_date] => 2010-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12727258 [rel_patent_id] =>[rel_patent_doc_number] =>)