Mark S. Blouin

Array ( [id] => 18064272 [patent_doc_number] => 20220395359 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-12-15 [patent_title] => Advanced Deep Learning Health Related Sensor Integration and Data Acquisition Apparatus, Method, and System [patent_app_type] => utility [patent_app_number] => 16/443878 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18064272 [patent_doc_number] => 20220395359 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-12-15 [patent_title] => Advanced Deep Learning Health Related Sensor Integration and Data Acquisition Apparatus, Method, and System [patent_app_type] => utility [patent_app_number] => 16/443878 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16574356 [patent_doc_number] => 10896280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Netlist abstraction for circuit design floorplanning [patent_app_type] => utility [patent_app_number] => 16/443696 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6695 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14901963 [patent_doc_number] => 20190294747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Clock Verification [patent_app_type] => utility [patent_app_number] => 16/441473 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16520970 [patent_doc_number] => 10872185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-22 [patent_title] => Systems and methods for estimating wire capacitance in a register-transfer level circuit design [patent_app_type] => utility [patent_app_number] => 16/441335 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4172 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16292475 [patent_doc_number] => 10769327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-08 [patent_title] => Integrated circuit authentication using mask fingerprinting [patent_app_type] => utility [patent_app_number] => 16/440295 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16574353 [patent_doc_number] => 10896277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Over-constraints for formal verification [patent_app_type] => utility [patent_app_number] => 16/440297 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14873079 [patent_doc_number] => 20190286781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => Hot Spot and Process Window Monitoring [patent_app_type] => utility [patent_app_number] => 16/431330 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17381660 [patent_doc_number] => 11239695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Wireless power system with device priority [patent_app_type] => utility [patent_app_number] => 16/421291 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8081 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15217665 [patent_doc_number] => 20190371519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SHIELD SHEET FOR WIRELESS CHARGING MODULE AND WIRELESS CHARGING MODULE [patent_app_type] => utility [patent_app_number] => 16/420536 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17018922 [patent_doc_number] => 11088572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Detachable charging pad [patent_app_type] => utility [patent_app_number] => 16/417594 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3616 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15155337 [patent_doc_number] => 20190356146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => INTEGRATED CHARGER AND REMOTE CONTROL [patent_app_type] => utility [patent_app_number] => 16/409655 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17211138 [patent_doc_number] => 11171522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Wireless charging efficiency [patent_app_type] => utility [patent_app_number] => 16/393526 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16217536 [patent_doc_number] => 10733350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => On-chip and system-area multi-processor interconnection networks in advanced processes for maximizing performance minimizing cost and energy [patent_app_type] => utility [patent_app_number] => 16/375684 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 13141 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16698996 [patent_doc_number] => 10949599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Overcoming retiming limitations due to initial conditions conflicts [patent_app_type] => utility [patent_app_number] => 16/370070 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17220174 [patent_doc_number] => 11172654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Aquarium [patent_app_type] => utility [patent_app_number] => 16/364501 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3706 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18129650 [patent_doc_number] => 11555854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Deterministic stellar built-in self test [patent_app_type] => utility [patent_app_number] => 16/982241 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16501704 [patent_doc_number] => 10867093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => System and method for an electronic design tool providing automated guidance and interface for circuit design processing [patent_app_type] => utility [patent_app_number] => 16/359800 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7024 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14571377 [patent_doc_number] => 20190213295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => METHODS AND APPARATUS FOR SECURE IMPLEMENTION OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/357759 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14571365 [patent_doc_number] => 20190213289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION AWARE SYSTEM ON A PROGRAMMABLE LOGIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/356713 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356713 [rel_patent_id] =>[rel_patent_doc_number] =>)