Mark S. Blouin

Array ( [id] => 19819548 [patent_doc_number] => 20250077755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => SEMICONDUCTOR DEVICE WITH REDACTED LOGIC [patent_app_type] => utility [patent_app_number] => 18/456648 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19951289 [patent_doc_number] => 12322660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Method and apparatus to determine a patterning process parameter [patent_app_type] => utility [patent_app_number] => 18/230115 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 57 [patent_no_of_words] => 47046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18787583 [patent_doc_number] => 20230375916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => INVERSE LITHOGRAPHY AND MACHINE LEARNING FOR MASK SYNTHESIS [patent_app_type] => utility [patent_app_number] => 18/228509 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748282 [patent_doc_number] => 20250036847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => APPLICATION OF MACHINE LEARNING TECHNIQUES TO INTELLECTUAL PROPERTY (IP) BASED DATA STRUCTURE FOR FUNCTIONAL SAFETY ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/226190 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19885961 [patent_doc_number] => 12271678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Integrated circuit with constrained metal line arrangement, method of using, and system for using [patent_app_type] => utility [patent_app_number] => 18/357731 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925453 [patent_doc_number] => 20240028457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METHOD AND DEVICE FOR DETECTING ERRORS IN ROUTES AND CALCULATIONS WITHIN AN FPGA [patent_app_type] => utility [patent_app_number] => 18/224778 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18975339 [patent_doc_number] => 20240055431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => MULTI-THRESHOLD INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME [patent_app_type] => utility [patent_app_number] => 18/222734 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19933975 [patent_doc_number] => 12307180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Capacitance extraction systems based on machine learning models [patent_app_type] => utility [patent_app_number] => 18/221370 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5156 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19695266 [patent_doc_number] => 20250013811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MODIFYING NETLISTS FOR DEVICE CHANGES IN IC DESIGNS [patent_app_type] => utility [patent_app_number] => 18/348149 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18710853 [patent_doc_number] => 20230333482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => METHOD FOR DECISION MAKING IN A SEMICONDUCTOR MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 18/212334 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18847389 [patent_doc_number] => 20230409793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => High-Level-Synthesis for RISC-V System-on-Chip Generation for Field Programmable Gate Arrays [patent_app_type] => utility [patent_app_number] => 18/208381 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18678320 [patent_doc_number] => 20230315968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => BOUNDARY CELL [patent_app_type] => utility [patent_app_number] => 18/331576 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18906586 [patent_doc_number] => 20240022071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => AIRPORT ELECTRIC VEHICLE CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/327044 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144947 [patent_doc_number] => 20240143883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => LAYOUT METHOD AND APPLICATION OF SCALABLE MULTI-DIE NETWORK-ON-CHIP FPGA ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/203662 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 1270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18695153 [patent_doc_number] => 20230325573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHOD AND SYSTEM FOR GENERATING LAYOUT DESIGN OF INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/327025 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19603572 [patent_doc_number] => 20240394452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => METHODS, DEVICES AND SYSTEMS FOR ANALOG CIRCUIT BLOCK OPERATIONS CONFIGURABLE WITH MEMORY-MAPPED ENTRIES [patent_app_type] => utility [patent_app_number] => 18/323228 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18788222 [patent_doc_number] => 20230376653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => Learning-Based Macro Placement with Quality of Human Experts [patent_app_type] => utility [patent_app_number] => 18/315904 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18695148 [patent_doc_number] => 20230325568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => QUANTUM CIRCUIT VALUATION [patent_app_type] => utility [patent_app_number] => 18/314206 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20790426 [patent_doc_number] => 12664342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Solution search system, solution search method, and solution search program [patent_app_type] => utility [patent_app_number] => 18/140426 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 29221 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19493401 [patent_doc_number] => 12112117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Method of manufacturing a semiconductor device including PG-aligned cells [patent_app_type] => utility [patent_app_number] => 18/308090 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308090 [rel_patent_id] =>[rel_patent_doc_number] =>)