Mark T Le
Examiner (ID: 16956, Phone: (571)272-6682 , Office: P/3617 )
Most Active Art Unit | 3617 |
Art Unit(s) | 3617, 3613, 3103, 3102, 3104 |
Total Applications | 3361 |
Issued Applications | 2650 |
Pending Applications | 119 |
Abandoned Applications | 591 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11725497
[patent_doc_number] => 09698364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-04
[patent_title] => 'Organic thin film transistor, preparing method thereof, and preparation equipment'
[patent_app_type] => utility
[patent_app_number] => 14/388544
[patent_app_country] => US
[patent_app_date] => 2013-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 7952
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14388544
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/388544 | Organic thin film transistor, preparing method thereof, and preparation equipment | Apr 6, 2013 | Issued |
Array
(
[id] => 9928327
[patent_doc_number] => 20150076519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-19
[patent_title] => 'VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD OF VERTICAL HIGH VOLTAGE SEMICONDUCTOR APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/388745
[patent_app_country] => US
[patent_app_date] => 2013-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7691
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14388745
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/388745 | Vertical high voltage semiconductor apparatus and fabrication method of vertical high voltage semiconductor apparatus | Mar 28, 2013 | Issued |
Array
(
[id] => 9768087
[patent_doc_number] => 20140291749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-02
[patent_title] => 'MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/852645
[patent_app_country] => US
[patent_app_date] => 2013-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3512
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852645
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/852645 | Memory device having multiple dielectric gate stacks and related methods | Mar 27, 2013 | Issued |
Array
(
[id] => 11765361
[patent_doc_number] => 09373819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-21
[patent_title] => 'Organic light-emitting device and method for producing an organic light-emitting device'
[patent_app_type] => utility
[patent_app_number] => 14/388784
[patent_app_country] => US
[patent_app_date] => 2013-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 10130
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14388784
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/388784 | Organic light-emitting device and method for producing an organic light-emitting device | Mar 18, 2013 | Issued |
Array
(
[id] => 9654247
[patent_doc_number] => 20140225252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'ON-TRACK REVERSE LITHOGRAPHY TO THIN MASK FOR FABRICATION OF DARK-FIELD FEATURES'
[patent_app_type] => utility
[patent_app_number] => 13/765429
[patent_app_country] => US
[patent_app_date] => 2013-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6471
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765429
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/765429 | ON-TRACK REVERSE LITHOGRAPHY TO THIN MASK FOR FABRICATION OF DARK-FIELD FEATURES | Feb 11, 2013 | Abandoned |
Array
(
[id] => 10518808
[patent_doc_number] => 09245862
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-01-26
[patent_title] => 'Electronic component package fabrication method and structure'
[patent_app_type] => utility
[patent_app_number] => 13/765388
[patent_app_country] => US
[patent_app_date] => 2013-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4678
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765388
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/765388 | Electronic component package fabrication method and structure | Feb 11, 2013 | Issued |
Array
(
[id] => 8960897
[patent_doc_number] => 20130200499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/757864
[patent_app_country] => US
[patent_app_date] => 2013-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3012
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757864
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757864 | SEMICONDUCTOR DEVICE | Feb 3, 2013 | Abandoned |
Array
(
[id] => 8960896
[patent_doc_number] => 20130200498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'METHODS AND APPARATUS FOR LITHOGRAPHY USING A RESIST ARRAY'
[patent_app_type] => utility
[patent_app_number] => 13/757820
[patent_app_country] => US
[patent_app_date] => 2013-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3735
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757820
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757820 | METHODS AND APPARATUS FOR LITHOGRAPHY USING A RESIST ARRAY | Feb 2, 2013 | Abandoned |
Array
(
[id] => 9972136
[patent_doc_number] => 09019152
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-28
[patent_title] => 'Standard wafer and its fabrication method'
[patent_app_type] => utility
[patent_app_number] => 13/757063
[patent_app_country] => US
[patent_app_date] => 2013-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4711
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757063
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757063 | Standard wafer and its fabrication method | Jan 31, 2013 | Issued |
Array
(
[id] => 8960871
[patent_doc_number] => 20130200473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'MICROMECHANICAL COMPONENT AND METHOD FOR THE MANUFACTURE OF SAME'
[patent_app_type] => utility
[patent_app_number] => 13/757261
[patent_app_country] => US
[patent_app_date] => 2013-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7337
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757261
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757261 | Micromechanical component and method for the manufacture of same | Jan 31, 2013 | Issued |
Array
(
[id] => 11678100
[patent_doc_number] => 09676614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-13
[patent_title] => 'MEMS device with stress relief structures'
[patent_app_type] => utility
[patent_app_number] => 13/757217
[patent_app_country] => US
[patent_app_date] => 2013-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 28
[patent_no_of_words] => 5943
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757217
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757217 | MEMS device with stress relief structures | Jan 31, 2013 | Issued |
Array
(
[id] => 8973740
[patent_doc_number] => 20130207170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-15
[patent_title] => 'PROGRAMMABLE LOGIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/754979
[patent_app_country] => US
[patent_app_date] => 2013-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 25443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754979
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754979 | Programmable logic device and method for manufacturing semiconductor device | Jan 30, 2013 | Issued |
Array
(
[id] => 11787528
[patent_doc_number] => 09396990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-19
[patent_title] => 'Capping layer for improved deposition selectivity'
[patent_app_type] => utility
[patent_app_number] => 13/755089
[patent_app_country] => US
[patent_app_date] => 2013-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5079
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755089
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/755089 | Capping layer for improved deposition selectivity | Jan 30, 2013 | Issued |
Array
(
[id] => 9000413
[patent_doc_number] => 20130221537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-29
[patent_title] => 'SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/754515
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2027
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754515
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754515 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS | Jan 29, 2013 | Abandoned |
Array
(
[id] => 9631991
[patent_doc_number] => 20140210099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'Packaged Semiconductor Devices and Packaging Methods'
[patent_app_type] => utility
[patent_app_number] => 13/754518
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7148
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754518
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754518 | Packaged semiconductor devices and packaging methods | Jan 29, 2013 | Issued |
Array
(
[id] => 9631911
[patent_doc_number] => 20140210019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'LOW-COST PACKAGE FOR INTEGRATED MEMS SENSORS'
[patent_app_type] => utility
[patent_app_number] => 13/753753
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2838
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753753
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753753 | LOW-COST PACKAGE FOR INTEGRATED MEMS SENSORS | Jan 29, 2013 | Abandoned |
Array
(
[id] => 9631960
[patent_doc_number] => 20140210068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN ETCHED SILICON WAFER TROUGHS FOR ENHANCED THERMAL PERFORMANCE'
[patent_app_type] => utility
[patent_app_number] => 13/754149
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10161
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754149
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754149 | Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance | Jan 29, 2013 | Issued |
Array
(
[id] => 10845124
[patent_doc_number] => 08872304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/754014
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 11014
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754014
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/754014 | Semiconductor device and method of manufacturing the same | Jan 29, 2013 | Issued |
Array
(
[id] => 9051369
[patent_doc_number] => 20130249083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'PACKAGING SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/753906
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3183
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753906
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753906 | PACKAGING SUBSTRATE | Jan 29, 2013 | Abandoned |
Array
(
[id] => 11725225
[patent_doc_number] => 09698090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-04
[patent_title] => 'Semiconductor substrate and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/753882
[patent_app_country] => US
[patent_app_date] => 2013-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2402
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753882
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753882 | Semiconductor substrate and fabrication method thereof | Jan 29, 2013 | Issued |