Search

Mark T Le

Examiner (ID: 16956, Phone: (571)272-6682 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3613, 3103, 3102, 3104
Total Applications
3361
Issued Applications
2650
Pending Applications
119
Abandoned Applications
591

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16410016 [patent_doc_number] => 10818580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Electronic component device [patent_app_type] => utility [patent_app_number] => 16/028735 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 55 [patent_no_of_words] => 11889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028735 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028735
Electronic component device Jul 5, 2018 Issued
Array ( [id] => 15791727 [patent_doc_number] => 10629595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Power semiconductor device having different gate crossings, and method for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/020133 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020133
Power semiconductor device having different gate crossings, and method for manufacturing thereof Jun 26, 2018 Issued
Array ( [id] => 13909231 [patent_doc_number] => 20190043820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => POWER ELECTRONICS ASSEMBLY HAVING AN ADHESION LAYER, AND METHOD FOR PRODUCING SAID ASSEMBLY [patent_app_type] => utility [patent_app_number] => 16/020378 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020378
Power electronics assembly having an adhesion layer, and method for producing said assembly Jun 26, 2018 Issued
Array ( [id] => 15331585 [patent_doc_number] => 20200006122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => INTEGRATED CIRCUITS (ICS) MADE USING EXTREME ULTRAVIOLET (EUV) PATTERNING AND METHODS FOR FABRICATING SUCH ICS [patent_app_type] => utility [patent_app_number] => 16/020096 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020096
INTEGRATED CIRCUITS (ICS) MADE USING EXTREME ULTRAVIOLET (EUV) PATTERNING AND METHODS FOR FABRICATING SUCH ICS Jun 26, 2018 Abandoned
Array ( [id] => 13500027 [patent_doc_number] => 20180301556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => VERTICAL TRANSISTORS WITH SIDEWALL GATE AIR GAPS AND METHODS THEREFOR [patent_app_type] => utility [patent_app_number] => 16/016219 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/016219
Vertical transistors with sidewall gate air gaps and methods therefor Jun 21, 2018 Issued
Array ( [id] => 14446387 [patent_doc_number] => 20190181067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/001181 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001181
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Jun 5, 2018 Abandoned
Array ( [id] => 16928360 [patent_doc_number] => 11049851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Method and system for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement [patent_app_type] => utility [patent_app_number] => 16/001135 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001135
Method and system for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement Jun 5, 2018 Issued
Array ( [id] => 15260121 [patent_doc_number] => 20190378794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/001083 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001083
BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS Jun 5, 2018 Abandoned
Array ( [id] => 15154331 [patent_doc_number] => 20190355643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => Wire Bonded Package with Single Piece Exposed Heat Slug and Leads [patent_app_type] => utility [patent_app_number] => 15/983621 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983621
Wire bonded package with single piece exposed heat slug and leads May 17, 2018 Issued
Array ( [id] => 16048061 [patent_doc_number] => 10685914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/983682 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 43 [patent_no_of_words] => 12005 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983682
Semiconductor device and manufacturing method thereof May 17, 2018 Issued
Array ( [id] => 15286467 [patent_doc_number] => 10515903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Selective CVD alignment-mark topography assist for non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/983689 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6605 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983689
Selective CVD alignment-mark topography assist for non-volatile memory May 17, 2018 Issued
Array ( [id] => 15791741 [patent_doc_number] => 10629602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Static random access memory cells with arranged vertical-transport field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/983627 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983627
Static random access memory cells with arranged vertical-transport field-effect transistors May 17, 2018 Issued
Array ( [id] => 13832533 [patent_doc_number] => 20190019751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => FUSE FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 15/978153 [patent_app_country] => US [patent_app_date] => 2018-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978153
FUSE FABRICATION METHOD May 12, 2018 Abandoned
Array ( [id] => 15123479 [patent_doc_number] => 20190348373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Semiconductor Device with Stress Relieving Structure [patent_app_type] => utility [patent_app_number] => 15/976653 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976653
Semiconductor Device with Stress Relieving Structure May 9, 2018 Abandoned
Array ( [id] => 15123471 [patent_doc_number] => 20190348369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD AND APPARATUS FOR PROTECTING METAL INTERCONNECT FROM HALOGEN BASED PRECURSORS [patent_app_type] => utility [patent_app_number] => 15/976507 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976507
METHOD AND APPARATUS FOR PROTECTING METAL INTERCONNECT FROM HALOGEN BASED PRECURSORS May 9, 2018 Abandoned
Array ( [id] => 15123787 [patent_doc_number] => 20190348527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Fin and Gate Dimensions for Optimizing Gate Formation [patent_app_type] => utility [patent_app_number] => 15/976664 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976664 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976664
Fin and gate dimensions for optimizing gate formation May 9, 2018 Issued
Array ( [id] => 15123459 [patent_doc_number] => 20190348363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR DEVICES HAVING ELECTROSTATIC DISCHARGE LAYOUTS FOR REDUCED CAPACITANCE [patent_app_type] => utility [patent_app_number] => 15/976674 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976674
Semiconductor devices having electrostatic discharge layouts for reduced capacitance May 9, 2018 Issued
Array ( [id] => 13629781 [patent_doc_number] => 20180366443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => FINER GRAIN DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 15/976580 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976580 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976580
Finer grain dynamic random access memory May 9, 2018 Issued
Array ( [id] => 15611387 [patent_doc_number] => 10586763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 15/966558 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966558
Semiconductor device and method of manufacture Apr 29, 2018 Issued
Array ( [id] => 15045733 [patent_doc_number] => 20190333871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MIXING ORGANIC MATERIALS INTO HYBRID PACKAGES [patent_app_type] => utility [patent_app_number] => 15/966630 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966630
Mixing organic materials into hybrid packages Apr 29, 2018 Issued
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