Search

Mark V. Prenty

Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2503, 2814, 2899, 2822
Total Applications
3023
Issued Applications
2591
Pending Applications
61
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16456303 [patent_doc_number] => 20200365729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/986810 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/986810
Semiconductor device Aug 5, 2020 Issued
Array ( [id] => 19095520 [patent_doc_number] => 11957004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => OLED display panel and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/047076 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17047076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/047076
OLED display panel and fabrication method thereof Aug 4, 2020 Issued
Array ( [id] => 18048173 [patent_doc_number] => 11522131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Resistive memory device and methods of making such a resistive memory device [patent_app_type] => utility [patent_app_number] => 16/945058 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4799 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945058
Resistive memory device and methods of making such a resistive memory device Jul 30, 2020 Issued
Array ( [id] => 16812550 [patent_doc_number] => 20210135105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING [patent_app_type] => utility [patent_app_number] => 16/939497 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939497
High electron affinity dielectric layer to improve cycling Jul 26, 2020 Issued
Array ( [id] => 16873663 [patent_doc_number] => 20210167130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/937963 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937963
Variable resistance memory device and method of fabricating the same Jul 23, 2020 Issued
Array ( [id] => 19973917 [patent_doc_number] => 12342550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Memory array structure [patent_app_type] => utility [patent_app_number] => 17/784652 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17784652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/784652
Memory array structure Jul 22, 2020 Issued
Array ( [id] => 16402526 [patent_doc_number] => 20200343384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => FinFETs and Methods of Forming FinFETs [patent_app_type] => utility [patent_app_number] => 16/927082 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927082
FinFETs and methods of forming FinFETs Jul 12, 2020 Issued
Array ( [id] => 17772588 [patent_doc_number] => 11404541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Binary III-nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications [patent_app_type] => utility [patent_app_number] => 16/926700 [patent_app_country] => US [patent_app_date] => 2020-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926700
Binary III-nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications Jul 10, 2020 Issued
Array ( [id] => 18373390 [patent_doc_number] => 11653583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Resistive random access memories and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/922253 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 5995 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922253
Resistive random access memories and method for fabricating the same Jul 6, 2020 Issued
Array ( [id] => 17011238 [patent_doc_number] => 20210242399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => TOP ELECTRODE VIA WITH LOW CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 16/921133 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921133
Top electrode via with low contact resistance Jul 5, 2020 Issued
Array ( [id] => 17319211 [patent_doc_number] => 20210408261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => VERTICAL TRANSISTOR HAVING AN OXYGEN-BLOCKING TOP SPACER [patent_app_type] => utility [patent_app_number] => 16/910296 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910296
Vertical transistor having an oxygen-blocking top spacer Jun 23, 2020 Issued
Array ( [id] => 16332494 [patent_doc_number] => 20200303460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => 1T1R RESISTIVE RANDOM ACCESS MEMORY,AND MANUFACTURING METHOD THEREOF, TRANSISTOR AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/896951 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896951
1T1R resistive random access memory, and manufacturing method thereof, transistor and device Jun 8, 2020 Issued
Array ( [id] => 16316380 [patent_doc_number] => 20200295118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/889908 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889908 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889908
Display device Jun 1, 2020 Issued
Array ( [id] => 16316124 [patent_doc_number] => 20200294862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => Methods for Improving Interlayer Dielectric Layer Topography [patent_app_type] => utility [patent_app_number] => 16/889381 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889381
Methods for improving interlayer dielectric layer topography May 31, 2020 Issued
Array ( [id] => 18446896 [patent_doc_number] => 11682471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Dual damascene crossbar array for disabling a defective resistive switching device in the array [patent_app_type] => utility [patent_app_number] => 16/885317 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6231 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885317
Dual damascene crossbar array for disabling a defective resistive switching device in the array May 27, 2020 Issued
Array ( [id] => 17681107 [patent_doc_number] => 11365347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Method for preparation of perovskite quantum dot (PQD)/polymer/ceramic ternary complex [patent_app_type] => utility [patent_app_number] => 16/885267 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7693 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885267
Method for preparation of perovskite quantum dot (PQD)/polymer/ceramic ternary complex May 27, 2020 Issued
Array ( [id] => 17263008 [patent_doc_number] => 20210375993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => HIGH DENSITY MEMORY DEVICES WITH LOW CELL LEAKAGE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/885346 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885346
High density memory devices with low cell leakage and methods for forming the same May 27, 2020 Issued
Array ( [id] => 16858419 [patent_doc_number] => 20210159164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/884447 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884447
Semiconductor device and method for manufacturing the same May 26, 2020 Issued
Array ( [id] => 16301251 [patent_doc_number] => 20200286974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DIODE DISPLAY [patent_app_type] => utility [patent_app_number] => 16/883367 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -49 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883367
Thin film transistor array substrate and organic light-emitting diode display May 25, 2020 Issued
Array ( [id] => 17270505 [patent_doc_number] => 11195936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/881685 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881685
Semiconductor structure May 21, 2020 Issued
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