Search

Mark V. Prenty

Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2503, 2814, 2899, 2822
Total Applications
3023
Issued Applications
2591
Pending Applications
61
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15823433 [patent_doc_number] => 10636916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => High electron mobility thin film transistors [patent_app_type] => utility [patent_app_number] => 15/999949 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 18438 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999949 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/999949
High electron mobility thin film transistors Sep 4, 2018 Issued
Array ( [id] => 14382153 [patent_doc_number] => 20190164989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/122037 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122037 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122037
Vertical type semiconductor devices and methods of manufacturing the same Sep 4, 2018 Issued
Array ( [id] => 16339410 [patent_doc_number] => 10790380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Semiconductor chip and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/121730 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 3987 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121730
Semiconductor chip and manufacturing method thereof Sep 4, 2018 Issued
Array ( [id] => 16280295 [patent_doc_number] => 10763336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/121346 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 35 [patent_no_of_words] => 11166 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121346
Semiconductor device and method for manufacturing the same Sep 3, 2018 Issued
Array ( [id] => 15673353 [patent_doc_number] => 10600920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/121220 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5482 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121220
Semiconductor device Sep 3, 2018 Issued
Array ( [id] => 15703387 [patent_doc_number] => 10607880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Die with buried doped isolation region [patent_app_type] => utility [patent_app_number] => 16/116986 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116986 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116986
Die with buried doped isolation region Aug 29, 2018 Issued
Array ( [id] => 15234635 [patent_doc_number] => 10505048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Self-aligned source/drain contact for vertical field effect transistor [patent_app_type] => utility [patent_app_number] => 16/117221 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6128 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117221
Self-aligned source/drain contact for vertical field effect transistor Aug 29, 2018 Issued
Array ( [id] => 15984645 [patent_doc_number] => 10672658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/116949 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116949
Semiconductor device and method of forming the same Aug 29, 2018 Issued
Array ( [id] => 15519707 [patent_doc_number] => 10566452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Semiconductor device and control device [patent_app_type] => utility [patent_app_number] => 16/117392 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5831 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117392
Semiconductor device and control device Aug 29, 2018 Issued
Array ( [id] => 15376179 [patent_doc_number] => 10529818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Semiconductor device with reduced flicker noise [patent_app_type] => utility [patent_app_number] => 16/117166 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 7212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117166
Semiconductor device with reduced flicker noise Aug 29, 2018 Issued
Array ( [id] => 15331645 [patent_doc_number] => 20200006152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Methods for Improving Interlayer Dielectric Layer Topography [patent_app_type] => utility [patent_app_number] => 16/117241 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117241
Methods for improving interlayer dielectric layer topography Aug 29, 2018 Issued
Array ( [id] => 16432874 [patent_doc_number] => 10832971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Fabricating tapered semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/117258 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117258
Fabricating tapered semiconductor devices Aug 29, 2018 Issued
Array ( [id] => 16433074 [patent_doc_number] => 10833173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Low-resistance top contact on VTFET [patent_app_type] => utility [patent_app_number] => 16/117106 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5829 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117106
Low-resistance top contact on VTFET Aug 29, 2018 Issued
Array ( [id] => 15332461 [patent_doc_number] => 20200006560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SOURCE/DRAIN EPITAXIAL LAYER PROFILE [patent_app_type] => utility [patent_app_number] => 16/117064 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117064
Source/drain epitaxial layer profile Aug 29, 2018 Issued
Array ( [id] => 17115982 [patent_doc_number] => 20210296579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 17/250553 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250553
RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR PREPARING THE SAME Aug 1, 2018 Abandoned
Array ( [id] => 13558909 [patent_doc_number] => 20180331002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/033054 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033054 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033054
ELECTRONIC DEVICE Jul 10, 2018 Abandoned
Array ( [id] => 13485369 [patent_doc_number] => 20180294227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/004573 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004573
Semiconductor package structure Jun 10, 2018 Issued
Array ( [id] => 13667865 [patent_doc_number] => 10164114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => FinFETs and methods of forming FinFETs [patent_app_type] => utility [patent_app_number] => 15/991680 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 54 [patent_no_of_words] => 7348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991680 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991680
FinFETs and methods of forming FinFETs May 28, 2018 Issued
Array ( [id] => 19476116 [patent_doc_number] => 12106211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Mixed signal neuromorphic computing with nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 16/608006 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 56 [patent_no_of_words] => 16049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16608006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/608006
Mixed signal neuromorphic computing with nonvolatile memory devices Apr 26, 2018 Issued
Array ( [id] => 16080341 [patent_doc_number] => 20200194157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => MAGNETIZATION CONTROL ELEMENT, MAGNETIC MEMORY, AND MAGNETIC RECORDING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/606271 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606271
Magnetization control element, magnetic memory, and magnetic recording system Apr 19, 2018 Issued
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