Mark V. Prenty

Array ( [id] => 14333143 [patent_doc_number] => 10297600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/956287 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 13988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16264722 [patent_doc_number] => 10756170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => VFET devices with improved performance [patent_app_type] => utility [patent_app_number] => 15/954663 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7607 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13528585 [patent_doc_number] => 20180315835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS [patent_app_type] => utility [patent_app_number] => 15/948563 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13528583 [patent_doc_number] => 20180315834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS [patent_app_type] => utility [patent_app_number] => 15/948554 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14005257 [patent_doc_number] => 10221064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Semiconductor package with multiple compartments [patent_app_type] => utility [patent_app_number] => 15/934267 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12918016 [patent_doc_number] => 20180197848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES WITH A DISTRIBUTED TRIGGER CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/914387 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15169985 [patent_doc_number] => 10490496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/904346 [patent_app_country] => US [patent_app_date] => 2018-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8353 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14125549 [patent_doc_number] => 10249638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/904349 [patent_app_country] => US [patent_app_date] => 2018-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 79 [patent_no_of_words] => 15270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14827915 [patent_doc_number] => 10410972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Integrated module with electromagnetic shielding [patent_app_type] => utility [patent_app_number] => 15/903243 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5972 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13571399 [patent_doc_number] => 20180337247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => METHOD TO IMPROVE HKMG CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 15/904175 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16356706 [patent_doc_number] => 10797224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Magnetoresistive device and method of fabricating same [patent_app_type] => utility [patent_app_number] => 15/904189 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10409 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14285063 [patent_doc_number] => 20190139816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR STRUCTURE INCLUDING ISOLATIONS AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/902422 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12849574 [patent_doc_number] => 20180175031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/895987 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14859405 [patent_doc_number] => 10418438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Capacitor structure with an extended dielectric layer and method of forming a capacitor structure [patent_app_type] => utility [patent_app_number] => 15/885948 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676491 [patent_doc_number] => 20190237360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => NANOSHEET STRUCTURE WITH ISOLATED GATE [patent_app_type] => utility [patent_app_number] => 15/885926 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13470473 [patent_doc_number] => 20180286779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/885830 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676895 [patent_doc_number] => 20190237562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => Techniques for Vertical FET Gate Length Control [patent_app_type] => utility [patent_app_number] => 15/886539 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14125519 [patent_doc_number] => 10249623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 15/886447 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 16585 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14573397 [patent_doc_number] => 20190214306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/885834 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13435241 [patent_doc_number] => 20180269163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/885837 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885837 [rel_patent_id] =>[rel_patent_doc_number] =>)