Mark V. Prenty

Array ( [id] => 15286613 [patent_doc_number] => 10515976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/885878 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3458 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13832571 [patent_doc_number] => 20190019770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => PASSIVATION SCHEME FOR PAD OPENINGS AND TRENCHES [patent_app_type] => utility [patent_app_number] => 15/883797 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12823813 [patent_doc_number] => 20180166443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 15/878990 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15234749 [patent_doc_number] => 10505105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Magnetoresistive effect element [patent_app_type] => utility [patent_app_number] => 16/081357 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16081357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15488767 [patent_doc_number] => 10559749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Magnetoresistive effect element [patent_app_type] => utility [patent_app_number] => 16/081192 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6081 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16081192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13306829 [patent_doc_number] => 20180204951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => VERTICAL TRANSISTORS WITH IMPROVED TOP SOURCE/DRAIN JUNCTIONS [patent_app_type] => utility [patent_app_number] => 15/872256 [patent_app_country] => US [patent_app_date] => 2018-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15872256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921823 [patent_doc_number] => 10205036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Array of Geiger-mode avalanche photodiodes for detecting infrared radiation [patent_app_type] => utility [patent_app_number] => 15/868929 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17493572 [patent_doc_number] => 11282889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Substrate for a front-side-type image sensor and method for producing such a substrate [patent_app_type] => utility [patent_app_number] => 16/477499 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 4267 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13528565 [patent_doc_number] => 20180315825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => VERTICAL FIN WITH A GATE STRUCTURE HAVING A MODIFIED GATE GEOMETRY [patent_app_type] => utility [patent_app_number] => 15/861137 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15401307 [patent_doc_number] => 10541316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Contact over active gate structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859412 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73868 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12615342 [patent_doc_number] => 20180096944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/819117 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13293737 [patent_doc_number] => 10158069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Memory cell having resistance variable film and method of making the same [patent_app_type] => utility [patent_app_number] => 15/817916 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769639 [patent_doc_number] => 10177169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Semiconductor device structure with 110-PFET and 111-NFET current flow direction [patent_app_type] => utility [patent_app_number] => 15/800489 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4451 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14558471 [patent_doc_number] => 10347708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => OLED display panel and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/798620 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3434 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12181784 [patent_doc_number] => 20180040720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'FINFET Structure and Method for Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 15/785764 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14769177 [patent_doc_number] => 10395990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/718482 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 57 [patent_no_of_words] => 12912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14110431 [patent_doc_number] => 20190096891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => IC INCLUDING STANDARD CELLS AND SRAM CELLS [patent_app_type] => utility [patent_app_number] => 15/718344 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14110185 [patent_doc_number] => 20190096768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/718752 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17825991 [patent_doc_number] => 11430948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Resistive random access memory device with switching multi-layer stack and methods of fabrication [patent_app_type] => utility [patent_app_number] => 16/641588 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16641588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14801071 [patent_doc_number] => 10403545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Power reduction in finFET structures [patent_app_type] => utility [patent_app_number] => 15/718740 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 8257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718740 [rel_patent_id] =>[rel_patent_doc_number] =>)