Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16180367 [patent_doc_number] => 20200227336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => PACKAGE WITH THERMAL INTERFACE MATERIAL RETAINING STRUCTURES ON DIE AND HEAT SPREADER [patent_app_type] => utility [patent_app_number] => 16/651329 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/651329
Package with thermal interface material retaining structures on die and heat spreader Sep 29, 2017 Issued
Array ( [id] => 14859113 [patent_doc_number] => 10418291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Induced warpage of a thermal conductor [patent_app_type] => utility [patent_app_number] => 15/720499 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720499
Induced warpage of a thermal conductor Sep 28, 2017 Issued
Array ( [id] => 16233992 [patent_doc_number] => 10741556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Self-aligned sacrificial epitaxial capping for trench silicide [patent_app_type] => utility [patent_app_number] => 15/719014 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2948 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719014
Self-aligned sacrificial epitaxial capping for trench silicide Sep 27, 2017 Issued
Array ( [id] => 13242909 [patent_doc_number] => 10134663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/714801 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 11113 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714801
Semiconductor device Sep 24, 2017 Issued
Array ( [id] => 14049727 [patent_doc_number] => 20190080971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => TESTING METHOD OF PACKAGING PROCESS AND PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/705250 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705250
Testing method of packaging process and packaging structure Sep 13, 2017 Issued
Array ( [id] => 14049535 [patent_doc_number] => 20190080875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => THERMALLY ASSISTED NEGATIVE ELECTRON AFFINITY PHOTOCATHODE [patent_app_type] => utility [patent_app_number] => 15/702647 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702647
Thermally assisted negative electron affinity photocathode Sep 11, 2017 Issued
Array ( [id] => 14049735 [patent_doc_number] => 20190080975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => MULTI-MOLDINGS FAN-OUT PACKAGE AND PROCESS [patent_app_type] => utility [patent_app_number] => 15/701394 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701394
Multi-moldings fan-out package and process Sep 10, 2017 Issued
Array ( [id] => 15634013 [patent_doc_number] => 10589983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Silicon carbide microelectromechanical structure, device, and method [patent_app_type] => utility [patent_app_number] => 15/698604 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 11804 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698604
Silicon carbide microelectromechanical structure, device, and method Sep 6, 2017 Issued
Array ( [id] => 15134527 [patent_doc_number] => 10480720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Active illumination source and PCB components having mountings for reduced Z-height and improved thermal conductivity [patent_app_type] => utility [patent_app_number] => 15/679547 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5330 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679547
Active illumination source and PCB components having mountings for reduced Z-height and improved thermal conductivity Aug 16, 2017 Issued
Array ( [id] => 13963205 [patent_doc_number] => 20190057947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/679666 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679666
Molded semiconductor package and related methods Aug 16, 2017 Issued
Array ( [id] => 12849076 [patent_doc_number] => 20180174865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => FAN-OUT STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/678788 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678788
Fan-out structure and method of fabricating the same Aug 15, 2017 Issued
Array ( [id] => 13963195 [patent_doc_number] => 20190057942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => INTEGRATED CIRCUIT WITH AN EMBEDDED INDUCTOR OR TRANSFORMER [patent_app_type] => utility [patent_app_number] => 15/678841 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678841
Integrated circuit with an embedded inductor or transformer Aug 15, 2017 Issued
Array ( [id] => 14093949 [patent_doc_number] => 10242887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Semiconductor device and method of making embedded wafer level chip scale packages [patent_app_type] => utility [patent_app_number] => 15/674247 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 76 [patent_no_of_words] => 14262 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674247
Semiconductor device and method of making embedded wafer level chip scale packages Aug 9, 2017 Issued
Array ( [id] => 16653379 [patent_doc_number] => 10930572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Method for manufacturing a three dimensional power module [patent_app_type] => utility [patent_app_number] => 16/322766 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322766
Method for manufacturing a three dimensional power module Jul 27, 2017 Issued
Array ( [id] => 12162686 [patent_doc_number] => 20180033952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/646399 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/646399
Electronic device and method of fabricating the same Jul 10, 2017 Issued
Array ( [id] => 12141116 [patent_doc_number] => 20180019199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYER WITH COPPER MIGRATION STOPPING' [patent_app_type] => utility [patent_app_number] => 15/644403 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644403
SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYER WITH COPPER MIGRATION STOPPING Jul 6, 2017 Abandoned
Array ( [id] => 12129267 [patent_doc_number] => 20180012853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'CHIP PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/643012 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5685 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643012
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Jul 5, 2017 Abandoned
Array ( [id] => 14429707 [patent_doc_number] => 10319667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Electronic device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/642284 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642284
Electronic device and method of fabricating the same Jul 4, 2017 Issued
Array ( [id] => 15687983 [patent_doc_number] => 20200098655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => ENCLOSURE FOR AN ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 16/619061 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16619061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/619061
Enclosure for an electronic component Jun 29, 2017 Issued
Array ( [id] => 17137711 [patent_doc_number] => 11139278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module [patent_app_type] => utility [patent_app_number] => 16/621700 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 9868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16621700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/621700
Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module Jun 26, 2017 Issued
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