Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10787436 [patent_doc_number] => 20160133592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 14/936837 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9432 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936837 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/936837
Semiconductor device and manufacturing method for the same Nov 9, 2015 Issued
Array ( [id] => 11623158 [patent_doc_number] => 20170133345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'BONDING SUBSTRATES USING SOLDER SURFACE TENSION DURING SOLDER REFLOW FOR THREE DIMENSIONAL SELF-ALIGNMENT OF SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 14/936849 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6695 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/936849
Bonding substrates using solder surface tension during solder reflow for three dimensional self-alignment of substrates Nov 9, 2015 Issued
Array ( [id] => 10718076 [patent_doc_number] => 20160064223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'METHOD OF FORMING METAL GATE ELECTRODE' [patent_app_type] => utility [patent_app_number] => 14/936939 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/936939
Method of forming metal gate electrode Nov 9, 2015 Issued
Array ( [id] => 11637923 [patent_doc_number] => 09659908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-23 [patent_title] => 'Systems and methods for package on package through mold interconnects' [patent_app_type] => utility [patent_app_number] => 14/937022 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937022 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/937022
Systems and methods for package on package through mold interconnects Nov 9, 2015 Issued
Array ( [id] => 11623147 [patent_doc_number] => 20170133334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/935912 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935912
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Nov 8, 2015 Abandoned
Array ( [id] => 11753421 [patent_doc_number] => 09711440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Wiring board and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/935749 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 10261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935749
Wiring board and method for manufacturing the same Nov 8, 2015 Issued
Array ( [id] => 11459990 [patent_doc_number] => 20170053896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'PACKAGE STRUCTURES AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/935160 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 8749 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935160
Package structures and method of forming the same Nov 5, 2015 Issued
Array ( [id] => 10787657 [patent_doc_number] => 20160133813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'On-Chip Thermoelectric Generator' [patent_app_type] => utility [patent_app_number] => 14/934895 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3526 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/934895
On-chip thermoelectric generator Nov 5, 2015 Issued
Array ( [id] => 12935644 [patent_doc_number] => 09831104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-28 [patent_title] => Techniques for molded underfill for integrated circuit dies [patent_app_type] => utility [patent_app_number] => 14/935011 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4036 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935011 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935011
Techniques for molded underfill for integrated circuit dies Nov 5, 2015 Issued
Array ( [id] => 14801189 [patent_doc_number] => 10403604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Stacked package assembly with voltage reference plane [patent_app_type] => utility [patent_app_number] => 15/766150 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 4714 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15766150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/766150
Stacked package assembly with voltage reference plane Nov 4, 2015 Issued
Array ( [id] => 10709943 [patent_doc_number] => 20160056090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'TSV Formation' [patent_app_type] => utility [patent_app_number] => 14/933583 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14933583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/933583
TSV formation Nov 4, 2015 Issued
Array ( [id] => 10703242 [patent_doc_number] => 20160049389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => '3DIC Package and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/925404 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 4113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925404
3DIC package and methods of forming the same Oct 27, 2015 Issued
Array ( [id] => 10725753 [patent_doc_number] => 20160071901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'IMAGING DEVICE AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/923937 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5151 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/923937
Imaging device and imaging system Oct 26, 2015 Issued
Array ( [id] => 10689494 [patent_doc_number] => 20160035641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT' [patent_app_type] => utility [patent_app_number] => 14/875917 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3281 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875917
SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT Oct 5, 2015 Abandoned
Array ( [id] => 10754327 [patent_doc_number] => 20160100479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/872850 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872850
DISPLAY DEVICE Sep 30, 2015 Abandoned
Array ( [id] => 12040443 [patent_doc_number] => 09818679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/871742 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 11713 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/871742
Semiconductor device Sep 29, 2015 Issued
Array ( [id] => 11532733 [patent_doc_number] => 20170092713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'ORIENTATION ENGINEERING IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIN FIELD EFFECT TRANSISTOR INTEGRATION FOR INCREASED MOBILITY AND SHARPER JUNCTION' [patent_app_type] => utility [patent_app_number] => 14/865667 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865667 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865667
Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction Sep 24, 2015 Issued
Array ( [id] => 11118054 [patent_doc_number] => 20160315028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/856546 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856546 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/856546
Multi-chip package structure, wafer level chip package structure and manufacturing process thereof Sep 15, 2015 Issued
Array ( [id] => 10747397 [patent_doc_number] => 20160093548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SEMICONDUCTOR PACKAGE WITH PRINTED SENSOR' [patent_app_type] => utility [patent_app_number] => 14/849026 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849026
Semiconductor package with printed sensor Sep 8, 2015 Issued
Array ( [id] => 10486929 [patent_doc_number] => 20150371949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'ELECTROLESS FILLED CONDUCTIVE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/841018 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8459 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841018 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841018
ELECTROLESS FILLED CONDUCTIVE STRUCTURES Aug 30, 2015 Abandoned
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