Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10624469 [patent_doc_number] => 09343419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Bump structures for semiconductor package' [patent_app_type] => utility [patent_app_number] => 13/787465 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5952 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787465
Bump structures for semiconductor package Mar 5, 2013 Issued
Array ( [id] => 10563513 [patent_doc_number] => 09287194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Packaging devices and methods for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/787714 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 7246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787714 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787714
Packaging devices and methods for semiconductor devices Mar 5, 2013 Issued
Array ( [id] => 9778640 [patent_doc_number] => 08853849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Package arrangement and a method of manufacturing a package arrangement' [patent_app_type] => utility [patent_app_number] => 13/786525 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6972 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786525
Package arrangement and a method of manufacturing a package arrangement Mar 5, 2013 Issued
Array ( [id] => 10118661 [patent_doc_number] => 09153549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/005941 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8862 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14005941 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/005941
Semiconductor device Feb 11, 2013 Issued
Array ( [id] => 9428289 [patent_doc_number] => 08704369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Flip chip bump structure and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/765152 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 7526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765152
Flip chip bump structure and fabrication method Feb 11, 2013 Issued
Array ( [id] => 8880918 [patent_doc_number] => 20130154102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD' [patent_app_type] => utility [patent_app_number] => 13/764532 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6860 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764532 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764532
Semiconductor device and its manufacture method Feb 10, 2013 Issued
Array ( [id] => 8863315 [patent_doc_number] => 20130147018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'Structure for Reducing Integrated Circuit Corner Peeling' [patent_app_type] => utility [patent_app_number] => 13/764478 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764478
Structure for reducing integrated circuit corner peeling Feb 10, 2013 Issued
Array ( [id] => 10964670 [patent_doc_number] => 20140367701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/356488 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4142 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356488
Semiconductor device Jan 9, 2013 Issued
Array ( [id] => 8821610 [patent_doc_number] => 20130122655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Embedded Wafer-Level Bonding Approaches' [patent_app_type] => utility [patent_app_number] => 13/734651 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3022 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734651
Embedded wafer-level bonding approaches Jan 3, 2013 Issued
Array ( [id] => 8819009 [patent_doc_number] => 20130120054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'DIE POWER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/732048 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4491 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/732048
Die power structure Dec 30, 2012 Issued
Array ( [id] => 11599575 [patent_doc_number] => 09646747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Chip component' [patent_app_type] => utility [patent_app_number] => 14/373900 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 192 [patent_figures_cnt] => 228 [patent_no_of_words] => 144243 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14373900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/373900
Chip component Dec 25, 2012 Issued
Array ( [id] => 8792184 [patent_doc_number] => 20130109153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'MULTIPLE SEAL RING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/725123 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725123
Multiple seal ring structure Dec 20, 2012 Issued
Array ( [id] => 8826004 [patent_doc_number] => 20130127049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Method for Stacking Devices and Structure Thereof' [patent_app_type] => utility [patent_app_number] => 13/716844 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716844
Method for Stacking Devices and Structure Thereof Dec 16, 2012 Abandoned
Array ( [id] => 9783091 [patent_doc_number] => 20140299911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'Method for Producing Optoelectronic Semiconductor Components, Lead Frame Composite, and Optoelectronic Semiconductor Component' [patent_app_type] => utility [patent_app_number] => 14/356554 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356554 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356554
Method for producing optoelectronic semiconductor components, lead frame composite, and optoelectronic semiconductor component Dec 12, 2012 Issued
Array ( [id] => 9608079 [patent_doc_number] => 08785244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Wafer level packaging using a lead-frame' [patent_app_type] => utility [patent_app_number] => 13/689416 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4964 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689416
Wafer level packaging using a lead-frame Nov 28, 2012 Issued
Array ( [id] => 8733238 [patent_doc_number] => 20130078807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/680668 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6708 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680668 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680668
WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME Nov 18, 2012 Abandoned
Array ( [id] => 11252970 [patent_doc_number] => 09478481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Semiconductor device, method for manufacturing same, and electronic component' [patent_app_type] => utility [patent_app_number] => 14/345234 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 40 [patent_no_of_words] => 10781 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14345234 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/345234
Semiconductor device, method for manufacturing same, and electronic component Nov 13, 2012 Issued
Array ( [id] => 8897225 [patent_doc_number] => 08476748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Exposed die overmolded flip chip package and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/665295 [patent_app_country] => US [patent_app_date] => 2012-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/665295
Exposed die overmolded flip chip package and fabrication method Oct 30, 2012 Issued
Array ( [id] => 10604068 [patent_doc_number] => 09324638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Compact wirebonded power quad flat no-lead (PQFN) package' [patent_app_type] => utility [patent_app_number] => 13/662244 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662244
Compact wirebonded power quad flat no-lead (PQFN) package Oct 25, 2012 Issued
Array ( [id] => 9216252 [patent_doc_number] => 08629052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Methods of forming semiconductor devices having narrow conductive line patterns' [patent_app_type] => utility [patent_app_number] => 13/652550 [patent_app_country] => US [patent_app_date] => 2012-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 14080 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652550
Methods of forming semiconductor devices having narrow conductive line patterns Oct 15, 2012 Issued
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