Mark V Prenty

Array ( [id] => 8610258 [patent_doc_number] => 20130015570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/411061 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9621393 [patent_doc_number] => 08791568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-29 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/410658 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2167 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9000393 [patent_doc_number] => 20130221517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SEMICONDUCTOR WORKPIECE WITH BACKSIDE METALLIZATION AND METHODS OF DICING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/408102 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2829 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13408102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9376403 [patent_doc_number] => 08680668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Device including a semiconductor chip and metal foils' [patent_app_type] => utility [patent_app_number] => 13/407157 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 49 [patent_no_of_words] => 8854 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8359109 [patent_doc_number] => 20120214279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR CHIP STACK' [patent_app_type] => utility [patent_app_number] => 13/400558 [patent_app_country] => US [patent_app_date] => 2012-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3907 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13400558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9608083 [patent_doc_number] => 08785248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Wafer level packaging using a lead-frame' [patent_app_type] => utility [patent_app_number] => 13/346443 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4280 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13346443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9937261 [patent_doc_number] => 08987066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Processing unit comprising integrated circuits including a common configuration of electrical interconnects' [patent_app_type] => utility [patent_app_number] => 13/342707 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9996569 [patent_doc_number] => 09041171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Programmable interposer with conductive particles' [patent_app_type] => utility [patent_app_number] => 13/340430 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3603 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8275080 [patent_doc_number] => 20120168939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'CHIP PACKAGE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/340162 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3612 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8154938 [patent_doc_number] => 20120098145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/340485 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20120098145.pdf [firstpage_image] =>[orig_patent_app_number] => 13340485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9335136 [patent_doc_number] => 20140061918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'METHOD OF FORMING LOW RESISTIVITY TaNx/Ta DIFFUSION BARRIERS FOR BACKEND INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 13/995170 [patent_app_country] => US [patent_app_date] => 2011-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5289 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10842885 [patent_doc_number] => 08870047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Wafer dicing press and method and semiconductor wafer dicing system including the same' [patent_app_type] => utility [patent_app_number] => 13/336218 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5255 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13336218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8994939 [patent_doc_number] => 08518823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Through silicon via and method of forming the same' [patent_app_type] => utility [patent_app_number] => 13/335948 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3817 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9195398 [patent_doc_number] => 20130334713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'ELECTROSTATIC DISCHARGE COMPLIANT PATTERNED ADHESIVE TAPE' [patent_app_type] => utility [patent_app_number] => 13/993339 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3664 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9091392 [patent_doc_number] => 20130270703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'ELECTROLESS FILLED CONDUCTIVE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/976084 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8403 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8249154 [patent_doc_number] => 20120153475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD OF ASSEMBLING TWO INTEGRATED CIRCUITS AND CORRESPONDING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/328175 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3263 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153475.pdf [firstpage_image] =>[orig_patent_app_number] => 13328175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8880926 [patent_doc_number] => 20130154110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'DIRECT WRITE INTERCONNECTIONS AND METHOD OF MANUFACTURING THEREOF' [patent_app_type] => utility [patent_app_number] => 13/328359 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4193 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13328359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8880925 [patent_doc_number] => 20130154109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/328332 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6298 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13328332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8863347 [patent_doc_number] => 20130147050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SEMICONDUCTOR HAVING INTEGRALLY-FORMED ENHANCED THERMAL MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/316906 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5553 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10537789 [patent_doc_number] => 09263424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Semiconductor chip stacking assemblies' [patent_app_type] => utility [patent_app_number] => 13/977242 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2862 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977242 [rel_patent_id] =>[rel_patent_doc_number] =>)