
Mark V. Prenty
Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2503, 2814, 2899, 2822 |
| Total Applications | 3023 |
| Issued Applications | 2591 |
| Pending Applications | 61 |
| Abandoned Applications | 386 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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