Search

Mark V. Prenty

Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2503, 2814, 2899, 2822
Total Applications
3023
Issued Applications
2591
Pending Applications
61
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20163155 [patent_doc_number] => 12389814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => High electron affinity dielectric layer to improve cycling [patent_app_type] => utility [patent_app_number] => 17/880835 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 8322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880835
High electron affinity dielectric layer to improve cycling Aug 3, 2022 Issued
Array ( [id] => 19973970 [patent_doc_number] => 12342604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Fin isolation structures of semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/875009 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875009
Fin isolation structures of semiconductor devices Jul 26, 2022 Issued
Array ( [id] => 17993714 [patent_doc_number] => 20220359751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SOURCE/DRAIN EPITAXIAL LAYER PROFILE [patent_app_type] => utility [patent_app_number] => 17/815063 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815063
Source/drain epitaxial layer profile Jul 25, 2022 Issued
Array ( [id] => 17993719 [patent_doc_number] => 20220359756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => FinFETs and Methods of Forming FinFETs [patent_app_type] => utility [patent_app_number] => 17/814681 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814681
FinFETs and methods of forming FinFETs Jul 24, 2022 Issued
Array ( [id] => 17993786 [patent_doc_number] => 20220359823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => TOP ELECTRODE VIA WITH LOW CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/868968 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868968
Top electrode via with low contact resistance Jul 19, 2022 Issued
Array ( [id] => 18009043 [patent_doc_number] => 20220367810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => RESISTIVE MEMORY CELL HAVING A LOW FORMING VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/867973 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867973
Resistive memory cell having a low forming voltage Jul 18, 2022 Issued
Array ( [id] => 18913135 [patent_doc_number] => 11876124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Vertical transistor having an oxygen-blocking layer [patent_app_type] => utility [patent_app_number] => 17/811129 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811129
Vertical transistor having an oxygen-blocking layer Jul 6, 2022 Issued
Array ( [id] => 18113288 [patent_doc_number] => 20230006168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ORGANIC DEVICE AND MANUFACTURING METHOD FOR ORGANIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/809579 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809579
Organic device and manufacturing method for organic device Jun 28, 2022 Issued
Array ( [id] => 18410598 [patent_doc_number] => 20230171951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/809667 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809667
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Jun 28, 2022 Pending
Array ( [id] => 18097475 [patent_doc_number] => 20220415816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => WAFER-LEVEL ASIC 3D INTEGRATED SUBSTRATE, PACKAGING DEVICE AND PREPARATION METHOD [patent_app_type] => utility [patent_app_number] => 17/851752 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851752
Wafer-level ASIC 3D integrated substrate, packaging device and preparation method Jun 27, 2022 Issued
Array ( [id] => 20404451 [patent_doc_number] => 12494432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/843899 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 1185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843899
Semiconductor structure and method for forming the same Jun 16, 2022 Issued
Array ( [id] => 19010261 [patent_doc_number] => 20240074332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => ATOMICALLY TUNED ULTRATHIN MEMRISTORS [patent_app_type] => utility [patent_app_number] => 18/280305 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18280305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/280305
Atomically tuned ultrathin memristors May 30, 2022 Issued
Array ( [id] => 19974057 [patent_doc_number] => 12342692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Display device, electronic device, and fabricating method of the display device [patent_app_type] => utility [patent_app_number] => 17/748217 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748217
Display device, electronic device, and fabricating method of the display device May 18, 2022 Issued
Array ( [id] => 20390883 [patent_doc_number] => 12490634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Display panel [patent_app_type] => utility [patent_app_number] => 17/779604 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2394 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17779604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/779604
Display panel May 18, 2022 Issued
Array ( [id] => 19900274 [patent_doc_number] => 12278212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Reworkable inter-substrate bond structure [patent_app_type] => utility [patent_app_number] => 17/663857 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663857
Reworkable inter-substrate bond structure May 17, 2022 Issued
Array ( [id] => 20080867 [patent_doc_number] => 12354944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Three-dimensional memory device containing plural metal oxide blocking dielectric layers and method of making thereof [patent_app_type] => utility [patent_app_number] => 17/663055 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 51 [patent_no_of_words] => 16788 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663055
Three-dimensional memory device containing plural metal oxide blocking dielectric layers and method of making thereof May 11, 2022 Issued
Array ( [id] => 19873778 [patent_doc_number] => 12266649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Method for manufacturing semiconductor device with substrate for electrical connection [patent_app_type] => utility [patent_app_number] => 17/743044 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8479 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743044
Method for manufacturing semiconductor device with substrate for electrical connection May 11, 2022 Issued
Array ( [id] => 18983545 [patent_doc_number] => 11908733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Substrate processing method and device manufactured by using the same [patent_app_type] => utility [patent_app_number] => 17/741401 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741401
Substrate processing method and device manufactured by using the same May 9, 2022 Issued
Array ( [id] => 19842694 [patent_doc_number] => 12255094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/739114 [patent_app_country] => US [patent_app_date] => 2022-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739114
Semiconductor device May 6, 2022 Issued
Array ( [id] => 18783909 [patent_doc_number] => 11825716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/712222 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3501 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712222 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712222
Display device Apr 3, 2022 Issued
Menu