Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7666890 [patent_doc_number] => 20110316159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'CHIP STACK PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/224670 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224670
Chip stack package Sep 1, 2011 Issued
Array ( [id] => 7577335 [patent_doc_number] => 20110291217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'PHOTOELECTRIC CONVERTER AND IMAGING SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/207272 [patent_app_country] => US [patent_app_date] => 2011-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5095 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291217.pdf [firstpage_image] =>[orig_patent_app_number] => 13207272 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207272
PHOTOELECTRIC CONVERTER AND IMAGING SYSTEM INCLUDING THE SAME Aug 9, 2011 Abandoned
Array ( [id] => 9000414 [patent_doc_number] => 20130221539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH A THROUGH-CONTACT AND SEMICONDUCTOR COMPONENT WITH THROUGH-CONTACT' [patent_app_type] => utility [patent_app_number] => 13/820998 [patent_app_country] => US [patent_app_date] => 2011-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4320 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13820998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/820998
Method for producing a semiconductor component with a through-contact and semiconductor component with through-contact Aug 8, 2011 Issued
Array ( [id] => 9234230 [patent_doc_number] => 08599539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Ceramic chip assembly' [patent_app_type] => utility [patent_app_number] => 13/193836 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6758 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193836
Ceramic chip assembly Jul 28, 2011 Issued
Array ( [id] => 8634855 [patent_doc_number] => 20130026658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION' [patent_app_type] => utility [patent_app_number] => 13/193911 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3312 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193911 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193911
WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION Jul 28, 2011 Abandoned
Array ( [id] => 9677592 [patent_doc_number] => 08816505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Low stress vias' [patent_app_type] => utility [patent_app_number] => 13/193814 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 13747 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193814
Low stress vias Jul 28, 2011 Issued
Array ( [id] => 7815206 [patent_doc_number] => 20120061826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/192065 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061826.pdf [firstpage_image] =>[orig_patent_app_number] => 13192065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192065
Semiconductor device Jul 26, 2011 Issued
Array ( [id] => 8634827 [patent_doc_number] => 20130026630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'FLIP CHIPS HAVING MULTIPLE SOLDER BUMP GEOMETRIES' [patent_app_type] => utility [patent_app_number] => 13/191632 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1705 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191632
FLIP CHIPS HAVING MULTIPLE SOLDER BUMP GEOMETRIES Jul 26, 2011 Abandoned
Array ( [id] => 9676789 [patent_doc_number] => 08815698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Well region formation method and semiconductor base' [patent_app_type] => utility [patent_app_number] => 13/381636 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6017 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13381636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/381636
Well region formation method and semiconductor base Jul 25, 2011 Issued
Array ( [id] => 8634838 [patent_doc_number] => 20130026641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/189623 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189623
CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE Jul 24, 2011 Abandoned
Array ( [id] => 8634834 [patent_doc_number] => 20130026637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/189732 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4131 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189732 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189732
Metal gate electrode of a field effect transistor Jul 24, 2011 Issued
Array ( [id] => 8943970 [patent_doc_number] => 08497148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'MEMS devices and methods of forming same' [patent_app_type] => utility [patent_app_number] => 13/189057 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189057 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189057
MEMS devices and methods of forming same Jul 21, 2011 Issued
Array ( [id] => 7787809 [patent_doc_number] => 20120049365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/189157 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049365.pdf [firstpage_image] =>[orig_patent_app_number] => 13189157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189157
Semiconductor package Jul 21, 2011 Issued
Array ( [id] => 8615399 [patent_doc_number] => 20130020711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'Interconnect Pillars with Directed Compliance Geometry' [patent_app_type] => utility [patent_app_number] => 13/187694 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187694 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187694
Interconnect pillars with directed compliance geometry Jul 20, 2011 Issued
Array ( [id] => 8871172 [patent_doc_number] => 08466551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/187711 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187711 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187711
Semiconductor device Jul 20, 2011 Issued
Array ( [id] => 8933205 [patent_doc_number] => 08492907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/186000 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 20350 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186000 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186000
Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device Jul 18, 2011 Issued
Array ( [id] => 8615411 [patent_doc_number] => 20130020723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'COMPOSITE LAYERED CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/184971 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23729 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184971 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184971
Composite layered chip package Jul 17, 2011 Issued
Array ( [id] => 8676100 [patent_doc_number] => 08384216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Package structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/184578 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3128 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184578
Package structure and manufacturing method thereof Jul 17, 2011 Issued
Array ( [id] => 8955772 [patent_doc_number] => 08501544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation' [patent_app_type] => utility [patent_app_number] => 13/185384 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 5447 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185384
Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation Jul 17, 2011 Issued
Array ( [id] => 10195734 [patent_doc_number] => 09224647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer' [patent_app_type] => utility [patent_app_number] => 13/184253 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 7288 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184253 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184253
Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer Jul 14, 2011 Issued
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