Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7480535 [patent_doc_number] => 20110233545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'Semiconductor Chip Having Double Bump Structure And Smart Card Including The Same' [patent_app_type] => utility [patent_app_number] => 12/986801 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233545.pdf [firstpage_image] =>[orig_patent_app_number] => 12986801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986801
Semiconductor chip having double bump structure and smart card including the same Jan 6, 2011 Issued
Array ( [id] => 8237470 [patent_doc_number] => 20120146207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP' [patent_app_type] => utility [patent_app_number] => 12/986184 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3441 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986184
Stacked structure and stacked method for three-dimensional chip Jan 6, 2011 Issued
Array ( [id] => 8287440 [patent_doc_number] => 20120175772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'ALTERNATIVE SURFACE FINISHES FOR FLIP-CHIP BALL GRID ARRAYS' [patent_app_type] => utility [patent_app_number] => 12/986584 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2203 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986584 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986584
ALTERNATIVE SURFACE FINISHES FOR FLIP-CHIP BALL GRID ARRAYS Jan 6, 2011 Abandoned
Array ( [id] => 8287437 [patent_doc_number] => 20120175763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 12/985484 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3701 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985484 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985484
INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY Jan 5, 2011 Abandoned
Array ( [id] => 8287451 [patent_doc_number] => 20120175774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PROTRUDING BOTTOMSIDE TIPS' [patent_app_type] => utility [patent_app_number] => 12/985823 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985823 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985823
Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips Jan 5, 2011 Issued
Array ( [id] => 10870934 [patent_doc_number] => 08896135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Encapsulation film, package structure utilizing the same, and method for forming the package structure' [patent_app_type] => utility [patent_app_number] => 12/984542 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984542
Encapsulation film, package structure utilizing the same, and method for forming the package structure Jan 3, 2011 Issued
Array ( [id] => 6153703 [patent_doc_number] => 20110156220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/978944 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19851 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156220.pdf [firstpage_image] =>[orig_patent_app_number] => 12978944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978944
Manufacturing method of semiconductor device and semiconductor device Dec 26, 2010 Issued
Array ( [id] => 8664998 [patent_doc_number] => 08378460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of batch trimming circuit elements' [patent_app_type] => utility [patent_app_number] => 12/978492 [patent_app_country] => US [patent_app_date] => 2010-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 55 [patent_no_of_words] => 11090 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978492
Method of batch trimming circuit elements Dec 23, 2010 Issued
Array ( [id] => 6153699 [patent_doc_number] => 20110156219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/977618 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4500 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156219.pdf [firstpage_image] =>[orig_patent_app_number] => 12977618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/977618
SEMICONDUCTOR DEVICE Dec 22, 2010 Abandoned
Array ( [id] => 7656907 [patent_doc_number] => 20110306176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'ALIGNMENT MARK FOR OPAQUE LAYER' [patent_app_type] => utility [patent_app_number] => 12/964430 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20110306176.pdf [firstpage_image] =>[orig_patent_app_number] => 12964430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964430
Alignment mark for opaque layer Dec 8, 2010 Issued
Array ( [id] => 8064779 [patent_doc_number] => 20110244632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Reduction of Mechanical Stress in Metal Stacks of Sophisticated Semiconductor Devices During Die-Substrate Soldering by an Enhanced Cool Down Regime' [patent_app_type] => utility [patent_app_number] => 12/963134 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20110244632.pdf [firstpage_image] =>[orig_patent_app_number] => 12963134 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963134
Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime Dec 7, 2010 Issued
Array ( [id] => 6119684 [patent_doc_number] => 20110076803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'WAFER-LEVEL STACK PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/962934 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4228 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076803.pdf [firstpage_image] =>[orig_patent_app_number] => 12962934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962934
Wafer-level stack package Dec 7, 2010 Issued
Array ( [id] => 7711212 [patent_doc_number] => 20120003793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'METHOD FOR MANUFACTURING EMBEDDED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/963346 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2268 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963346 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963346
METHOD FOR MANUFACTURING EMBEDDED SUBSTRATE Dec 7, 2010 Abandoned
Array ( [id] => 8533887 [patent_doc_number] => 08310044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/962625 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 89 [patent_no_of_words] => 32540 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 514 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12962625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962625
Semiconductor device and method of manufacturing the same Dec 6, 2010 Issued
Array ( [id] => 6114509 [patent_doc_number] => 20110073984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'SEMICONDUCTOR POWER MODULE PACKAGE WITH TEMPERATURE SENSOR MOUNTED THEREON AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/962196 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4806 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20110073984.pdf [firstpage_image] =>[orig_patent_app_number] => 12962196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962196
Semiconductor power module package with temperature sensor mounted thereon and method of fabricating the same Dec 6, 2010 Issued
Array ( [id] => 6119683 [patent_doc_number] => 20110076802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'EMBEDDED CHIP PACKAGE PROCESS' [patent_app_type] => utility [patent_app_number] => 12/960547 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3612 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076802.pdf [firstpage_image] =>[orig_patent_app_number] => 12960547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960547
Embedded chip package process Dec 5, 2010 Issued
Array ( [id] => 6137537 [patent_doc_number] => 20110127647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/956635 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14383 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20110127647.pdf [firstpage_image] =>[orig_patent_app_number] => 12956635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/956635
Semiconductor device and method for making the same Nov 29, 2010 Issued
Array ( [id] => 9038446 [patent_doc_number] => 20130241084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/989962 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3039 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13989962 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/989962
Semiconductor device Nov 28, 2010 Issued
Array ( [id] => 8205265 [patent_doc_number] => 20120126395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die' [patent_app_type] => utility [patent_app_number] => 12/949396 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7024 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126395.pdf [firstpage_image] =>[orig_patent_app_number] => 12949396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949396
Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die Nov 17, 2010 Issued
Array ( [id] => 7773158 [patent_doc_number] => 20120038028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'MULTIPLE SEAL RING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/938272 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20120038028.pdf [firstpage_image] =>[orig_patent_app_number] => 12938272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938272
Multiple seal ring structure Nov 1, 2010 Issued
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