
Mark V. Prenty
Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2503, 2814, 2899, 2822 |
| Total Applications | 3023 |
| Issued Applications | 2591 |
| Pending Applications | 61 |
| Abandoned Applications | 386 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5145680
[patent_doc_number] => 20070045734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Thin film transistor and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/214677
[patent_app_country] => US
[patent_app_date] => 2005-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2696
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20070045734.pdf
[firstpage_image] =>[orig_patent_app_number] => 11214677
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/214677 | Thin film transistor and fabrication method thereof | Aug 28, 2005 | Issued |
Array
(
[id] => 6931341
[patent_doc_number] => 20050282376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Method of making a semiconductor device having improved contacts'
[patent_app_type] => utility
[patent_app_number] => 11/213267
[patent_app_country] => US
[patent_app_date] => 2005-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4428
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0282/20050282376.pdf
[firstpage_image] =>[orig_patent_app_number] => 11213267
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/213267 | Method of making a semiconductor device having improved contacts | Aug 25, 2005 | Issued |
Array
(
[id] => 5708071
[patent_doc_number] => 20060049415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Monolithic multi-color, multi-quantum well semiconductor LED'
[patent_app_type] => utility
[patent_app_number] => 11/210847
[patent_app_country] => US
[patent_app_date] => 2005-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3404
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20060049415.pdf
[firstpage_image] =>[orig_patent_app_number] => 11210847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/210847 | Monolithic multi-color, multi-quantum well semiconductor LED | Aug 24, 2005 | Issued |
Array
(
[id] => 9083992
[patent_doc_number] => RE044538
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2013-10-15
[patent_title] => 'Indium gallium nitride channel high electron mobility transistors, and method of making the same'
[patent_app_type] => reissue
[patent_app_number] => 11/211122
[patent_app_country] => US
[patent_app_date] => 2005-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2058
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11211122
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/211122 | Indium gallium nitride channel high electron mobility transistors, and method of making the same | Aug 23, 2005 | Issued |
Array
(
[id] => 5790907
[patent_doc_number] => 20060011982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Micro-mechanically strained semiconductor film'
[patent_app_type] => utility
[patent_app_number] => 11/210927
[patent_app_country] => US
[patent_app_date] => 2005-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6256
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20060011982.pdf
[firstpage_image] =>[orig_patent_app_number] => 11210927
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/210927 | Micro-mechanically strained semiconductor film | Aug 23, 2005 | Issued |
Array
(
[id] => 5868970
[patent_doc_number] => 20060163587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Packaging designs for LEDs'
[patent_app_type] => utility
[patent_app_number] => 11/209957
[patent_app_country] => US
[patent_app_date] => 2005-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9997
[patent_no_of_claims] => 95
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20060163587.pdf
[firstpage_image] =>[orig_patent_app_number] => 11209957
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/209957 | Packaging designs for LEDs | Aug 22, 2005 | Issued |
Array
(
[id] => 491343
[patent_doc_number] => 07214963
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-08
[patent_title] => '3-D column select circuit layout in semiconductor memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/206437
[patent_app_country] => US
[patent_app_date] => 2005-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3394
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/214/07214963.pdf
[firstpage_image] =>[orig_patent_app_number] => 11206437
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/206437 | 3-D column select circuit layout in semiconductor memory devices | Aug 17, 2005 | Issued |
Array
(
[id] => 5151971
[patent_doc_number] => 20070034853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Structures for reducing operating voltage in a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/203917
[patent_app_country] => US
[patent_app_date] => 2005-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6908
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20070034853.pdf
[firstpage_image] =>[orig_patent_app_number] => 11203917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/203917 | Structures for reducing operating voltage in a semiconductor device | Aug 14, 2005 | Issued |
Array
(
[id] => 5152062
[patent_doc_number] => 20070034944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Power LDMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 11/202968
[patent_app_country] => US
[patent_app_date] => 2005-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6261
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20070034944.pdf
[firstpage_image] =>[orig_patent_app_number] => 11202968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202968 | Power LDMOS transistor | Aug 11, 2005 | Issued |
Array
(
[id] => 5908955
[patent_doc_number] => 20060125015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'ESD protection for high voltage applications'
[patent_app_type] => utility
[patent_app_number] => 11/198277
[patent_app_country] => US
[patent_app_date] => 2005-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6661
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20060125015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11198277
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/198277 | ESD protection for high voltage applications | Aug 7, 2005 | Issued |
Array
(
[id] => 5796506
[patent_doc_number] => 20060033183
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Cascode, cascode circuit and method for vertical integration of two bipolar transistors into a cascode arrangement'
[patent_app_type] => utility
[patent_app_number] => 11/198317
[patent_app_country] => US
[patent_app_date] => 2005-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3029
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20060033183.pdf
[firstpage_image] =>[orig_patent_app_number] => 11198317
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/198317 | Cascode, cascode circuit and method for vertical integration of two bipolar transistors into a cascode arrangement | Aug 7, 2005 | Issued |
Array
(
[id] => 5878024
[patent_doc_number] => 20060027848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Ferroelectric memory device and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/196287
[patent_app_country] => US
[patent_app_date] => 2005-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3985
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20060027848.pdf
[firstpage_image] =>[orig_patent_app_number] => 11196287
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196287 | Ferroelectric memory device and method of forming the same | Aug 3, 2005 | Abandoned |
Array
(
[id] => 881025
[patent_doc_number] => 07355208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-08
[patent_title] => 'Nitride-based semiconductor element and method of forming nitride-based semiconductor'
[patent_app_type] => utility
[patent_app_number] => 11/195637
[patent_app_country] => US
[patent_app_date] => 2005-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 33
[patent_no_of_words] => 9906
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/355/07355208.pdf
[firstpage_image] =>[orig_patent_app_number] => 11195637
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/195637 | Nitride-based semiconductor element and method of forming nitride-based semiconductor | Aug 2, 2005 | Issued |
Array
(
[id] => 401506
[patent_doc_number] => 07291872
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-06
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/193417
[patent_app_country] => US
[patent_app_date] => 2005-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 7786
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/291/07291872.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193417
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193417 | Semiconductor device and method for fabricating the same | Jul 31, 2005 | Issued |
Array
(
[id] => 5838179
[patent_doc_number] => 20060118837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Active pixel sensor having honeycomb structure'
[patent_app_type] => utility
[patent_app_number] => 11/193917
[patent_app_country] => US
[patent_app_date] => 2005-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2932
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20060118837.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193917 | Active pixel sensor having honeycomb structure | Jul 28, 2005 | Issued |
Array
(
[id] => 5145650
[patent_doc_number] => 20070045704
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same'
[patent_app_type] => utility
[patent_app_number] => 11/191837
[patent_app_country] => US
[patent_app_date] => 2005-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2851
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20070045704.pdf
[firstpage_image] =>[orig_patent_app_number] => 11191837
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/191837 | Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same | Jul 27, 2005 | Issued |
Array
(
[id] => 5713277
[patent_doc_number] => 20060076640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/191607
[patent_app_country] => US
[patent_app_date] => 2005-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3786
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20060076640.pdf
[firstpage_image] =>[orig_patent_app_number] => 11191607
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/191607 | Semiconductor device | Jul 27, 2005 | Abandoned |
Array
(
[id] => 5737382
[patent_doc_number] => 20060007772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 11/189548
[patent_app_country] => US
[patent_app_date] => 2005-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4603
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20060007772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11189548
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/189548 | Non-volatile memory device | Jul 24, 2005 | Abandoned |
Array
(
[id] => 5768027
[patent_doc_number] => 20060019438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/187967
[patent_app_country] => US
[patent_app_date] => 2005-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2151
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20060019438.pdf
[firstpage_image] =>[orig_patent_app_number] => 11187967
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/187967 | Semiconductor device and method of manufacturing the same | Jul 24, 2005 | Abandoned |
Array
(
[id] => 826788
[patent_doc_number] => 07402452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-22
[patent_title] => 'Gate oxide film structure for a solid state image pick-up device'
[patent_app_type] => utility
[patent_app_number] => 11/187937
[patent_app_country] => US
[patent_app_date] => 2005-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3772
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/402/07402452.pdf
[firstpage_image] =>[orig_patent_app_number] => 11187937
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/187937 | Gate oxide film structure for a solid state image pick-up device | Jul 24, 2005 | Issued |