Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18563045 [patent_doc_number] => 11728298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/459604 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 7203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459604
Semiconductor device and method for manufacturing the same Aug 26, 2021 Issued
Array ( [id] => 18212633 [patent_doc_number] => 20230058897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => THERMAL CONDUCTION LAYER [patent_app_type] => utility [patent_app_number] => 17/445248 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445248
THERMAL CONDUCTION LAYER Aug 16, 2021 Pending
Array ( [id] => 19063201 [patent_doc_number] => 11942453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Thermal management of three-dimensional integrated circuits [patent_app_type] => utility [patent_app_number] => 17/401676 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9475 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401676
Thermal management of three-dimensional integrated circuits Aug 12, 2021 Issued
Array ( [id] => 17262787 [patent_doc_number] => 20210375772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD FOR FORMING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/400731 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400731 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400731
Method for forming package structure Aug 11, 2021 Issued
Array ( [id] => 17247025 [patent_doc_number] => 20210366770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/397621 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397621
Contact structure for semiconductor device Aug 8, 2021 Issued
Array ( [id] => 18219531 [patent_doc_number] => 11594480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Structures with deformable conductors [patent_app_type] => utility [patent_app_number] => 17/395130 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 8198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395130
Structures with deformable conductors Aug 4, 2021 Issued
Array ( [id] => 17247182 [patent_doc_number] => 20210366927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 17/393664 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393664
Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies Aug 3, 2021 Issued
Array ( [id] => 18263136 [patent_doc_number] => 11610845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Semiconductor package and a method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/392705 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8606 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392705
Semiconductor package and a method of fabricating the same Aug 2, 2021 Issued
Array ( [id] => 18205507 [patent_doc_number] => 11587912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => High density pillar interconnect conversion with stack to substrate connection [patent_app_type] => utility [patent_app_number] => 17/383304 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 8928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/383304
High density pillar interconnect conversion with stack to substrate connection Jul 21, 2021 Issued
Array ( [id] => 17217952 [patent_doc_number] => 20210351290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/379446 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379446
Semiconductor device structure Jul 18, 2021 Issued
Array ( [id] => 18608105 [patent_doc_number] => 11749583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Electronic package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/379289 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3746 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379289
Electronic package and method for manufacturing the same Jul 18, 2021 Issued
Array ( [id] => 18857384 [patent_doc_number] => 11854979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/379000 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11396 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379000
Semiconductor device Jul 18, 2021 Issued
Array ( [id] => 17477414 [patent_doc_number] => 20220084918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/375929 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375929
Semiconductor device Jul 13, 2021 Issued
Array ( [id] => 18507554 [patent_doc_number] => 11705381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => High efficiency heat dissipation using thermal interface material film [patent_app_type] => utility [patent_app_number] => 17/375304 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 7726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375304
High efficiency heat dissipation using thermal interface material film Jul 13, 2021 Issued
Array ( [id] => 17203516 [patent_doc_number] => 20210343611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => METHOD FOR FORMING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/372814 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372814
Method for forming package structure Jul 11, 2021 Issued
Array ( [id] => 17188871 [patent_doc_number] => 20210335756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/369119 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369119
Semiconductor package Jul 6, 2021 Issued
Array ( [id] => 18112942 [patent_doc_number] => 20230005822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => POLYIMIDE BONDED BUS BAR FOR POWER DEVICE [patent_app_type] => utility [patent_app_number] => 17/365048 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365048
POLYIMIDE BONDED BUS BAR FOR POWER DEVICE Jun 30, 2021 Abandoned
Array ( [id] => 17630625 [patent_doc_number] => 20220165640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 17/361644 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361644
Semiconductor module Jun 28, 2021 Issued
Array ( [id] => 17174111 [patent_doc_number] => 20210327782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => METHODS AND APPARATUS TO PROVIDE ELECTRICAL SHIELDING FOR INTEGRATED CIRCUIT PACKAGES USING A THERMAL INTERFACE MATERIAL [patent_app_type] => utility [patent_app_number] => 17/359085 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359085
Methods and apparatus to provide electrical shielding for integrated circuit packages using a thermal interface material Jun 24, 2021 Issued
Array ( [id] => 17630620 [patent_doc_number] => 20220165635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/357184 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357184
Semiconductor package and method of manufacturing semiconductor package Jun 23, 2021 Issued
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