Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5346191 [patent_doc_number] => 20090001552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/770088 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4240 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001552.pdf [firstpage_image] =>[orig_patent_app_number] => 11770088 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770088
Semiconductor package having through holes for molding back side of package Jun 27, 2007 Issued
Array ( [id] => 5346172 [patent_doc_number] => 20090001533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'MULTI-CHIP PACKAGING IN A TSOP PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/769178 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3516 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001533.pdf [firstpage_image] =>[orig_patent_app_number] => 11769178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769178
MULTI-CHIP PACKAGING IN A TSOP PACKAGE Jun 26, 2007 Abandoned
Array ( [id] => 4849681 [patent_doc_number] => 20080315423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/767769 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4658 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315423.pdf [firstpage_image] =>[orig_patent_app_number] => 11767769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767769
Semiconductor device Jun 24, 2007 Issued
Array ( [id] => 4849694 [patent_doc_number] => 20080315436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SEMICONDUCTOR WAFER THAT SUPPORTS MULTIPLE PACKAGING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/766000 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5009 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315436.pdf [firstpage_image] =>[orig_patent_app_number] => 11766000 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/766000
SEMICONDUCTOR WAFER THAT SUPPORTS MULTIPLE PACKAGING TECHNIQUES Jun 19, 2007 Abandoned
Array ( [id] => 5088942 [patent_doc_number] => 20070228581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'UNIVERSAL CHIP PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/761299 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3219 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228581.pdf [firstpage_image] =>[orig_patent_app_number] => 11761299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761299
UNIVERSAL CHIP PACKAGE STRUCTURE Jun 10, 2007 Abandoned
Array ( [id] => 4474759 [patent_doc_number] => 07867888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Flip-chip package substrate and a method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/808028 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 3435 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867888.pdf [firstpage_image] =>[orig_patent_app_number] => 11808028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808028
Flip-chip package substrate and a method for fabricating the same Jun 5, 2007 Issued
Array ( [id] => 5228196 [patent_doc_number] => 20070290303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'DUAL LEADFRAME SEMICONDUCTOR DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/758569 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2191 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20070290303.pdf [firstpage_image] =>[orig_patent_app_number] => 11758569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758569
DUAL LEADFRAME SEMICONDUCTOR DEVICE PACKAGE Jun 4, 2007 Abandoned
Array ( [id] => 5026311 [patent_doc_number] => 20070267757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/798938 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2502 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267757.pdf [firstpage_image] =>[orig_patent_app_number] => 11798938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798938
Semiconductor device May 16, 2007 Abandoned
Array ( [id] => 5026296 [patent_doc_number] => 20070267742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Dual mosfet package' [patent_app_type] => utility [patent_app_number] => 11/797779 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267742.pdf [firstpage_image] =>[orig_patent_app_number] => 11797779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797779
Dual MOSFET package May 7, 2007 Issued
Array ( [id] => 5222927 [patent_doc_number] => 20070252193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Non-volatile memory devices including variable resistance material' [patent_app_type] => utility [patent_app_number] => 11/785478 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3860 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252193.pdf [firstpage_image] =>[orig_patent_app_number] => 11785478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785478
Non-volatile memory devices including variable resistance material Apr 17, 2007 Issued
Array ( [id] => 4487663 [patent_doc_number] => 07902655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Multichip package leadframe including electrical bussing' [patent_app_type] => utility [patent_app_number] => 11/695978 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6629 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902655.pdf [firstpage_image] =>[orig_patent_app_number] => 11695978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695978
Multichip package leadframe including electrical bussing Apr 2, 2007 Issued
Array ( [id] => 4876622 [patent_doc_number] => 20080150005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'MEMORY SYSTEM WITH DEPLETION GATE' [patent_app_type] => utility [patent_app_number] => 11/694089 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150005.pdf [firstpage_image] =>[orig_patent_app_number] => 11694089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694089
MEMORY SYSTEM WITH DEPLETION GATE Mar 29, 2007 Abandoned
Array ( [id] => 7596656 [patent_doc_number] => 07619926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'NAND flash memory with fixed charge' [patent_app_type] => utility [patent_app_number] => 11/692958 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5095 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619926.pdf [firstpage_image] =>[orig_patent_app_number] => 11692958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692958
NAND flash memory with fixed charge Mar 28, 2007 Issued
Array ( [id] => 4715292 [patent_doc_number] => 20080237814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'ISOLATED SOLDER PADS' [patent_app_type] => utility [patent_app_number] => 11/691429 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2948 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237814.pdf [firstpage_image] =>[orig_patent_app_number] => 11691429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691429
ISOLATED SOLDER PADS Mar 25, 2007 Abandoned
Array ( [id] => 4936356 [patent_doc_number] => 20080073670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Gallium nitride high electron mobility transistor having inner field-plate for high power applications' [patent_app_type] => utility [patent_app_number] => 11/716446 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3021 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20080073670.pdf [firstpage_image] =>[orig_patent_app_number] => 11716446 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716446
Gallium nitride high electron mobility transistor having inner field-plate for high power applications Mar 7, 2007 Abandoned
Array ( [id] => 352964 [patent_doc_number] => 07491987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Junction field effect thin film transistor' [patent_app_type] => utility [patent_app_number] => 11/705108 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491987.pdf [firstpage_image] =>[orig_patent_app_number] => 11705108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705108
Junction field effect thin film transistor Feb 11, 2007 Issued
Array ( [id] => 4795347 [patent_doc_number] => 20080006933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Heat-dissipating package structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/704599 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006933.pdf [firstpage_image] =>[orig_patent_app_number] => 11704599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704599
Heat-dissipating package structure and fabrication method thereof Feb 7, 2007 Abandoned
Array ( [id] => 4800513 [patent_doc_number] => 20080012100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLASHLESS LEADS' [patent_app_type] => utility [patent_app_number] => 11/670899 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012100.pdf [firstpage_image] =>[orig_patent_app_number] => 11670899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670899
Integrated circuit package system with flashless leads Feb 1, 2007 Issued
Array ( [id] => 5175146 [patent_doc_number] => 20070176204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/699426 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176204.pdf [firstpage_image] =>[orig_patent_app_number] => 11699426 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699426
Field effect transistor Jan 29, 2007 Abandoned
Array ( [id] => 7730948 [patent_doc_number] => 08102057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Via design for flux residue mitigation' [patent_app_type] => utility [patent_app_number] => 11/645908 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102057.pdf [firstpage_image] =>[orig_patent_app_number] => 11645908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645908
Via design for flux residue mitigation Dec 26, 2006 Issued
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