Search

Mark V Prenty

Examiner (ID: 1781, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2814, 2503, 2822, 2899
Total Applications
2970
Issued Applications
2517
Pending Applications
67
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5191985 [patent_doc_number] => 20070080467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/542128 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3451 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080467.pdf [firstpage_image] =>[orig_patent_app_number] => 11542128 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542128
Semiconductor device Oct 3, 2006 Issued
Array ( [id] => 4936464 [patent_doc_number] => 20080073778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'TWO-WAY HEAT EXTRACTION FROM PACKAGED SEMICONDUCTOR CHIPS' [patent_app_type] => utility [patent_app_number] => 11/535749 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4247 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20080073778.pdf [firstpage_image] =>[orig_patent_app_number] => 11535749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535749
TWO-WAY HEAT EXTRACTION FROM PACKAGED SEMICONDUCTOR CHIPS Sep 26, 2006 Abandoned
Array ( [id] => 5116890 [patent_doc_number] => 20070138604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'HEAT FIXTURE FOR WIRE BONDING' [patent_app_type] => utility [patent_app_number] => 11/534859 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2206 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138604.pdf [firstpage_image] =>[orig_patent_app_number] => 11534859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534859
HEAT FIXTURE FOR WIRE BONDING Sep 24, 2006 Abandoned
Array ( [id] => 5133784 [patent_doc_number] => 20070075413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/525868 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11888 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20070075413.pdf [firstpage_image] =>[orig_patent_app_number] => 11525868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525868
Semiconductor package Sep 24, 2006 Issued
Array ( [id] => 4937603 [patent_doc_number] => 20080074920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Nonvolatile Memory with Reduced Coupling Between Floating Gates' [patent_app_type] => utility [patent_app_number] => 11/534139 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9946 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074920.pdf [firstpage_image] =>[orig_patent_app_number] => 11534139 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534139
Nonvolatile Memory with Reduced Coupling Between Floating Gates Sep 20, 2006 Abandoned
Array ( [id] => 4919353 [patent_doc_number] => 20080067665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Via structure' [patent_app_type] => utility [patent_app_number] => 11/524108 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067665.pdf [firstpage_image] =>[orig_patent_app_number] => 11524108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524108
Via structure Sep 19, 2006 Abandoned
Array ( [id] => 4919327 [patent_doc_number] => 20080067639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK' [patent_app_type] => utility [patent_app_number] => 11/532508 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067639.pdf [firstpage_image] =>[orig_patent_app_number] => 11532508 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532508
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK Sep 14, 2006 Abandoned
Array ( [id] => 5171904 [patent_doc_number] => 20070072337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of manufacturing the organic electroluminescent display and organic electroluminescent display manufactured by the method' [patent_app_type] => utility [patent_app_number] => 11/521308 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8728 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072337.pdf [firstpage_image] =>[orig_patent_app_number] => 11521308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521308
Method of manufacturing the organic electroluminescent display and organic electroluminescent display manufactured by the method Sep 14, 2006 Issued
Array ( [id] => 4919328 [patent_doc_number] => 20080067640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK' [patent_app_type] => utility [patent_app_number] => 11/532509 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067640.pdf [firstpage_image] =>[orig_patent_app_number] => 11532509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532509
Integrated circuit package system with encapsulation lock Sep 14, 2006 Issued
Array ( [id] => 4701903 [patent_doc_number] => 20080061425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'CHIP PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/531688 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061425.pdf [firstpage_image] =>[orig_patent_app_number] => 11531688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531688
CHIP PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF Sep 12, 2006 Abandoned
Array ( [id] => 4648733 [patent_doc_number] => 20080035988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Trenched MOSFET device with trenched contacts' [patent_app_type] => utility [patent_app_number] => 11/518729 [patent_app_country] => US [patent_app_date] => 2006-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3197 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20080035988.pdf [firstpage_image] =>[orig_patent_app_number] => 11518729 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518729
Trenched MOSFET device with trenched contacts Sep 9, 2006 Issued
Array ( [id] => 4800519 [patent_doc_number] => 20080012106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'CHIP PACKAGE STRUCTURE AND FABRICATING METHOD THREROF' [patent_app_type] => utility [patent_app_number] => 11/530178 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3828 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012106.pdf [firstpage_image] =>[orig_patent_app_number] => 11530178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530178
CHIP PACKAGE STRUCTURE AND FABRICATING METHOD THREROF Sep 7, 2006 Abandoned
Array ( [id] => 5054450 [patent_doc_number] => 20070057371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/517219 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4084 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057371.pdf [firstpage_image] =>[orig_patent_app_number] => 11517219 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517219
Semiconductor device Sep 6, 2006 Abandoned
Array ( [id] => 152694 [patent_doc_number] => 07679126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Split gate type non-volatile memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/516098 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679126.pdf [firstpage_image] =>[orig_patent_app_number] => 11516098 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516098
Split gate type non-volatile memory device and method of manufacturing the same Sep 4, 2006 Issued
Array ( [id] => 4768768 [patent_doc_number] => 20080054424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/469239 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054424.pdf [firstpage_image] =>[orig_patent_app_number] => 11469239 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469239
Semiconductor package and method therefor Aug 30, 2006 Issued
Array ( [id] => 5014137 [patent_doc_number] => 20070257345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Package structure to reduce warpage' [patent_app_type] => utility [patent_app_number] => 11/508829 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1720 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20070257345.pdf [firstpage_image] =>[orig_patent_app_number] => 11508829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/508829
Package structure to reduce warpage Aug 23, 2006 Abandoned
Array ( [id] => 5088805 [patent_doc_number] => 20070228444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Semiconductor memory device having reference transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/504689 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7345 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228444.pdf [firstpage_image] =>[orig_patent_app_number] => 11504689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504689
Semiconductor memory device having reference transistor and method of manufacturing the same Aug 15, 2006 Issued
Array ( [id] => 4608730 [patent_doc_number] => 07993969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Method for producing a module with components stacked one above another' [patent_app_type] => utility [patent_app_number] => 11/463799 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4188 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/993/07993969.pdf [firstpage_image] =>[orig_patent_app_number] => 11463799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463799
Method for producing a module with components stacked one above another Aug 9, 2006 Issued
Array ( [id] => 4651634 [patent_doc_number] => 20080038890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHOD FOR IMPROVED TRENCH PROTECTION IN VERTICAL UMOSFET DEVICES' [patent_app_type] => utility [patent_app_number] => 11/463709 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2183 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038890.pdf [firstpage_image] =>[orig_patent_app_number] => 11463709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463709
METHOD FOR IMPROVED TRENCH PROTECTION IN VERTICAL UMOSFET DEVICES Aug 9, 2006 Abandoned
Array ( [id] => 5019500 [patent_doc_number] => 20070145466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Flash memory device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/498389 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2274 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145466.pdf [firstpage_image] =>[orig_patent_app_number] => 11498389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498389
Flash memory device and method for manufacturing the same Aug 2, 2006 Abandoned
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