
Mark V. Prenty
Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2503, 2814, 2899, 2822 |
| Total Applications | 3023 |
| Issued Applications | 2591 |
| Pending Applications | 61 |
| Abandoned Applications | 386 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1102737
[patent_doc_number] => 06815796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-09
[patent_title] => 'Composite module and process of producing same'
[patent_app_type] => B2
[patent_app_number] => 10/313037
[patent_app_country] => US
[patent_app_date] => 2002-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 65
[patent_no_of_words] => 11123
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/815/06815796.pdf
[firstpage_image] =>[orig_patent_app_number] => 10313037
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313037 | Composite module and process of producing same | Dec 5, 2002 | Issued |
Array
(
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[patent_doc_number] => 06680516
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-20
[patent_title] => 'Controlled thickness gate stack'
[patent_app_type] => B1
[patent_app_number] => 10/313267
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10313267
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313267 | Controlled thickness gate stack | Dec 5, 2002 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Method of manufacturing semiconductor substrate, semiconductor substrate, electro-optical apparatus and electronic equipment'
[patent_app_type] => new
[patent_app_number] => 10/307297
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[patent_app_date] => 2002-12-02
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Array
(
[id] => 1153196
[patent_doc_number] => 06770954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Semiconductor device with SI-GE layer-containing low resistance, tunable contact'
[patent_app_type] => B2
[patent_app_number] => 10/305147
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305147 | Semiconductor device with SI-GE layer-containing low resistance, tunable contact | Nov 26, 2002 | Issued |
Array
(
[id] => 6865255
[patent_doc_number] => 20030190781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS'
[patent_app_type] => new
[patent_app_number] => 10/305437
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305437 | Memory masking for periphery salicidation of active regions | Nov 25, 2002 | Issued |
Array
(
[id] => 717221
[patent_doc_number] => 07053487
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[patent_issue_date] => 2006-05-30
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/294937
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Array
(
[id] => 1249081
[patent_doc_number] => 06674104
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[patent_title] => 'Bipolar transistor'
[patent_app_type] => B2
[patent_app_number] => 10/275558
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10275558
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Array
(
[id] => 963971
[patent_doc_number] => 06949784
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Zero-cost non-volatile memory cell with write and erase features'
[patent_app_type] => utility
[patent_app_number] => 10/285977
[patent_app_country] => US
[patent_app_date] => 2002-11-01
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/285977 | Zero-cost non-volatile memory cell with write and erase features | Oct 31, 2002 | Issued |
Array
(
[id] => 1113720
[patent_doc_number] => 06803621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Oxygen barrier for cell container process'
[patent_app_type] => B2
[patent_app_number] => 10/286155
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/286155 | Oxygen barrier for cell container process | Oct 30, 2002 | Issued |
Array
(
[id] => 1193719
[patent_doc_number] => 06730940
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => 'Enhanced brightness light emitting device spot emitter'
[patent_app_type] => B1
[patent_app_number] => 10/283737
[patent_app_country] => US
[patent_app_date] => 2002-10-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/730/06730940.pdf
[firstpage_image] =>[orig_patent_app_number] => 10283737
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/283737 | Enhanced brightness light emitting device spot emitter | Oct 28, 2002 | Issued |
Array
(
[id] => 1288587
[patent_doc_number] => 06639284
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Compensated-well electrostatic discharge protection structure'
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[pdf_file] => patents/06/639/06639284.pdf
[firstpage_image] =>[orig_patent_app_number] => 10280829
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/280829 | Compensated-well electrostatic discharge protection structure | Oct 24, 2002 | Issued |
Array
(
[id] => 985462
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[patent_title] => 'Use of gate electrode workfunction to improve DRAM refresh'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279094 | Use of gate electrode workfunction to improve DRAM refresh | Oct 23, 2002 | Issued |
Array
(
[id] => 7159402
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[patent_title] => 'Semiconductor device having a U-shaped gate structure'
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Array
(
[id] => 7627854
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[patent_title] => 'Semiconductor device structure including multiple fets having different spacer widths'
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Array
(
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Array
(
[id] => 7632738
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Array
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Array
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Array
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Array
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