Search

Mark V. Prenty

Examiner (ID: 10336, Phone: (571)272-1843 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2503, 2814, 2899, 2822
Total Applications
3023
Issued Applications
2591
Pending Applications
61
Abandoned Applications
386

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4222705 [patent_doc_number] => 06087696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Stacked tunneling dielectric technology for improving data retention of EEPROM cell' [patent_app_type] => 1 [patent_app_number] => 9/086437 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3870 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087696.pdf [firstpage_image] =>[orig_patent_app_number] => 086437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086437
Stacked tunneling dielectric technology for improving data retention of EEPROM cell May 27, 1998 Issued
Array ( [id] => 4161143 [patent_doc_number] => 06104039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'P-type nitrogen compound semiconductor and method of manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/084187 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3516 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104039.pdf [firstpage_image] =>[orig_patent_app_number] => 084187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084187
P-type nitrogen compound semiconductor and method of manufacturing same May 25, 1998 Issued
Array ( [id] => 6883942 [patent_doc_number] => 20010038097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'THIN FILM TRANSISTORS, AND LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC APPARATUS USING THE SAME' [patent_app_type] => new [patent_app_number] => 09/077207 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9406 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038097.pdf [firstpage_image] =>[orig_patent_app_number] => 09077207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/077207
Thin film transistors, and liquid crystal display device and electronic apparatus using the same May 25, 1998 Issued
Array ( [id] => 1550911 [patent_doc_number] => 06346725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines' [patent_app_type] => B1 [patent_app_number] => 09/083770 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 5247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346725.pdf [firstpage_image] =>[orig_patent_app_number] => 09083770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083770
Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines May 21, 1998 Issued
Array ( [id] => 1428183 [patent_doc_number] => 06504218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Asymmetrical N-channel and P-channel devices' [patent_app_type] => B1 [patent_app_number] => 09/082013 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504218.pdf [firstpage_image] =>[orig_patent_app_number] => 09082013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082013
Asymmetrical N-channel and P-channel devices May 19, 1998 Issued
Array ( [id] => 4209924 [patent_doc_number] => 06078080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region' [patent_app_type] => 1 [patent_app_number] => 9/081847 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078080.pdf [firstpage_image] =>[orig_patent_app_number] => 081847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081847
Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region May 19, 1998 Issued
Array ( [id] => 4108310 [patent_doc_number] => 06100563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor device formed on SOI substrate' [patent_app_type] => 1 [patent_app_number] => 9/080257 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100563.pdf [firstpage_image] =>[orig_patent_app_number] => 080257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080257
Semiconductor device formed on SOI substrate May 17, 1998 Issued
Array ( [id] => 1505377 [patent_doc_number] => 06465840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Integrated structure comprising a patterned feature substantially of single grain polysilicon' [patent_app_type] => B1 [patent_app_number] => 09/072247 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2950 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465840.pdf [firstpage_image] =>[orig_patent_app_number] => 09072247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072247
Integrated structure comprising a patterned feature substantially of single grain polysilicon May 3, 1998 Issued
Array ( [id] => 4253161 [patent_doc_number] => 06137141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'MOS device and fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/069867 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4208 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137141.pdf [firstpage_image] =>[orig_patent_app_number] => 069867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069867
MOS device and fabrication method Apr 29, 1998 Issued
Array ( [id] => 4113120 [patent_doc_number] => 06057566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/069338 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057566.pdf [firstpage_image] =>[orig_patent_app_number] => 069338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069338
Semiconductor device Apr 28, 1998 Issued
Array ( [id] => 4189250 [patent_doc_number] => 06150686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor integrated circuit device with trench capacitor and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/063779 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 51 [patent_no_of_words] => 13526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150686.pdf [firstpage_image] =>[orig_patent_app_number] => 063779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063779
Semiconductor integrated circuit device with trench capacitor and method of manufacturing the same Apr 21, 1998 Issued
Array ( [id] => 4139778 [patent_doc_number] => 06121662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => '3-D CMOS transistors with high ESD reliability' [patent_app_type] => 1 [patent_app_number] => 9/062827 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2324 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121662.pdf [firstpage_image] =>[orig_patent_app_number] => 062827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062827
3-D CMOS transistors with high ESD reliability Apr 19, 1998 Issued
Array ( [id] => 4264798 [patent_doc_number] => 06204536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/061249 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 12617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204536.pdf [firstpage_image] =>[orig_patent_app_number] => 061249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061249
Semiconductor device and manufacturing method thereof Apr 16, 1998 Issued
09/051790 FIELD-CONTROLLED BIPOLAR TRANSISTOR Apr 16, 1998 Abandoned
Array ( [id] => 4413707 [patent_doc_number] => 06300661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate' [patent_app_type] => 1 [patent_app_number] => 9/060509 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5755 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300661.pdf [firstpage_image] =>[orig_patent_app_number] => 060509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060509
Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate Apr 13, 1998 Issued
Array ( [id] => 4376576 [patent_doc_number] => 06288431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/054399 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 95 [patent_no_of_words] => 27537 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288431.pdf [firstpage_image] =>[orig_patent_app_number] => 054399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054399
Semiconductor device and a method of manufacturing the same Apr 2, 1998 Issued
Array ( [id] => 4203328 [patent_doc_number] => 06013927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same' [patent_app_type] => 1 [patent_app_number] => 9/052859 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5533 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013927.pdf [firstpage_image] =>[orig_patent_app_number] => 052859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052859
Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same Mar 30, 1998 Issued
Array ( [id] => 4362483 [patent_doc_number] => 06175128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Process for building borderless bitline, wordline and DRAM structure and resulting structure' [patent_app_type] => 1 [patent_app_number] => 9/052538 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2860 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175128.pdf [firstpage_image] =>[orig_patent_app_number] => 052538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052538
Process for building borderless bitline, wordline and DRAM structure and resulting structure Mar 30, 1998 Issued
Array ( [id] => 4203425 [patent_doc_number] => 06013931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Semiconductor device and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 9/046657 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 34 [patent_no_of_words] => 2797 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013931.pdf [firstpage_image] =>[orig_patent_app_number] => 046657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046657
Semiconductor device and method for producing the same Mar 23, 1998 Issued
Array ( [id] => 4152138 [patent_doc_number] => 06064103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Device with a P-N junction and a means of reducing the risk of breakdown of the junction' [patent_app_type] => 1 [patent_app_number] => 9/043640 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064103.pdf [firstpage_image] =>[orig_patent_app_number] => 043640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/043640
Device with a P-N junction and a means of reducing the risk of breakdown of the junction Mar 19, 1998 Issued
Menu