Mark W. Regn

Array ( [id] => 10795197 [patent_doc_number] => 20160141354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'Patterned Back-Barrier for III-Nitride Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 14/540463 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10309439 [patent_doc_number] => 20150194440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'Nonvolatile Memory Devices And Methods Of Fabricating The Same' [patent_app_type] => utility [patent_app_number] => 14/539043 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10343583 [patent_doc_number] => 20150228588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Semiconductor Wafers Including Indications of Crystal Orientation and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/519788 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765209 [patent_doc_number] => 20160111366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/518050 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4930 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10725659 [patent_doc_number] => 20160071807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'METHODOLOGY TO ACHIEVE ZERO WARPAGE FOR IC PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/518887 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11524666 [patent_doc_number] => 09608078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Semiconductor device with improved field plate' [patent_app_type] => utility [patent_app_number] => 14/517285 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11687282 [patent_doc_number] => 09685332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Iterative self-aligned patterning' [patent_app_type] => utility [patent_app_number] => 14/517252 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4866 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12335388 [patent_doc_number] => 09947797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/496368 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 60 [patent_no_of_words] => 27439 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10800966 [patent_doc_number] => 20160147123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'ARRAY SUBSTRATE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/435923 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9875118 [patent_doc_number] => 08962385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'ReRAM device structure' [patent_app_type] => utility [patent_app_number] => 14/490062 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3216 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9789660 [patent_doc_number] => 20150001605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices' [patent_app_type] => utility [patent_app_number] => 14/487201 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3970 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11360172 [patent_doc_number] => 09536829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Programmable electrical fuse in keep out zone' [patent_app_type] => utility [patent_app_number] => 14/483258 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10402719 [patent_doc_number] => 20150287729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/483063 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3155 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12040509 [patent_doc_number] => 09818744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Leakage current suppression methods and related structures' [patent_app_type] => utility [patent_app_number] => 14/477491 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 38 [patent_no_of_words] => 11175 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10351009 [patent_doc_number] => 20150236014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'STACKED METAL OXIDE SEMICONDUCTOR (MOS) AND METAL OXIDE METAL (MOM) CAPACITOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/476086 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10718338 [patent_doc_number] => 20160064484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'LATERAL BIPOLAR JUNCTION TRANSISTORS ON A SILICON-ON-INSULATOR SUBSTRATE WITH A THIN DEVICE LAYER THICKNESS' [patent_app_type] => utility [patent_app_number] => 14/476007 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5604 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10378148 [patent_doc_number] => 20150263155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/475533 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12102204 [patent_doc_number] => 09859304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Manufacturing method of array substrate, array substrate and display device' [patent_app_type] => utility [patent_app_number] => 14/436995 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4370 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14436995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10165484 [patent_doc_number] => 09196716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Enhancement mode III-N HEMTs' [patent_app_type] => utility [patent_app_number] => 14/464639 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 8956 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14301009 [patent_doc_number] => 10290636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods [patent_app_type] => utility [patent_app_number] => 14/461769 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2025 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14461769 [rel_patent_id] =>[rel_patent_doc_number] =>)